LXR uboot/arch/x86/lib/pci

   1/*
   2 * (C) Copyright 2002
   3 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * Support for type PCI configuration cycles.
  26 * based on pci_indirect.c
  27 */
  28#include <common.h>
  29#include <asm/io.h>
  30#include <pci.h>
  31
  32#define cfg_read(val, addr, op)         (*val = op((int)(addr)))
  33#define cfg_write(val, addr, op)        op((val), (int)(addr))
  34
  35#define TYPE1_PCI_OP(rw, size, type, op, mask)                          \
  36static int                                                              \
  37type1_##rw##_config_##size(struct pci_controller *hose,                 \
  38                              pci_dev_t dev, int offset, type val)      \
  39{                                                                       \
  40        outl(dev | (offset & 0xfc) | 0x80000000, (int)hose->cfg_addr);  \
  41        cfg_##rw(val, hose->cfg_data + (offset & mask), op);            \
  42        return 0;                                                       \
  43}
  44
  45TYPE1_PCI_OP(read, byte, u8 *, inb, 3)
  46TYPE1_PCI_OP(read, word, u16 *, inw, 2)
  47TYPE1_PCI_OP(read, dword, u32 *, inl, 0)
  48
  49TYPE1_PCI_OP(write, byte, u8, outb, 3)
  50TYPE1_PCI_OP(write, word, u16, outw, 2)
  51TYPE1_PCI_OP(write, dword, u32, outl, 0)
  52
  53/* bus mapping constants (used for PCI core initialization) */
  54#define PCI_REG_ADDR            0x00000cf8
  55#define PCI_REG_DATA            0x00000cfc
  56
  57void pci_setup_type1(struct pci_controller *hose)
  58{
  59        pci_set_ops(hose,
  60                    type1_read_config_byte,
  61                    type1_read_config_word,
  62                    type1_read_config_dword,
  63                    type1_write_config_byte,
  64                    type1_write_config_word,
  65                    type1_write_config_dword);
  66
  67        hose->cfg_addr = (unsigned int *)PCI_REG_ADDR;
  68        hose->cfg_data = (unsigned char *)PCI_REG_DATA;
  69}
  70