LXR uboot/board/cm-bf548/video.c

   1/*
   2 * video.c - run splash screen on lcd
   3 *
   4 * Copyright (c) 2007-2008 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#include <stdarg.h>
  10#include <common.h>
  11#include <config.h>
  12#include <malloc.h>
  13#include <asm/blackfin.h>
  14#include <asm/gpio.h>
  15#include <asm/portmux.h>
  16#include <asm/mach-common/bits/dma.h>
  17#include <i2c.h>
  18#include <linux/types.h>
  19#include <stdio_dev.h>
  20
  21#ifdef CONFIG_VIDEO
  22
  23#define DMA_SIZE16      2
  24
  25#include <asm/mach-common/bits/eppi.h>
  26
  27#include <asm/bfin_logo_230x230.h>
  28
  29#define LCD_X_RES               480     /*Horizontal Resolution */
  30#define LCD_Y_RES               272     /* Vertical Resolution */
  31
  32#define LCD_BPP                 24      /* Bit Per Pixel */
  33#define LCD_PIXEL_SIZE          (LCD_BPP / 8)
  34#define DMA_BUS_SIZE            32
  35#define ACTIVE_VIDEO_MEM_OFFSET 0
  36
  37/*      -- Horizontal synchronizing --
  38 *
  39 * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
  40 * (LCY-W-06602A Page 9 of 22)
  41 *
  42 * Clock Frequency      1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
  43 *
  44 * Period               TH - 525 - Clock
  45 * Pulse width          THp - 41 - Clock
  46 * Horizontal period    THd - 480 - Clock
  47 * Back porch           THb - 2 - Clock
  48 * Front porch          THf - 2 - Clock
  49 *
  50 * -- Vertical synchronizing --
  51 * Period               TV - 286 - Line
  52 * Pulse width          TVp - 10 - Line
  53 * Vertical period      TVd - 272 - Line
  54 * Back porch           TVb - 2 - Line
  55 * Front porch          TVf - 2 - Line
  56 */
  57
  58#define LCD_CLK                 (8*1000*1000)   /* 8MHz */
  59
  60/* # active data to transfer after Horizontal Delay clock */
  61#define EPPI_HCOUNT             LCD_X_RES
  62
  63/* # active lines to transfer after Vertical Delay clock */
  64#define EPPI_VCOUNT             LCD_Y_RES
  65
  66/* Samples per Line = 480 (active data) + 45 (padding) */
  67#define EPPI_LINE               525
  68
  69/* Lines per Frame = 272 (active data) + 14 (padding) */
  70#define EPPI_FRAME              286
  71
  72/* FS1 (Hsync) Width (Typical)*/
  73#define EPPI_FS1W_HBL           41
  74
  75/* FS1 (Hsync) Period (Typical) */
  76#define EPPI_FS1P_AVPL          EPPI_LINE
  77
  78/* Horizontal Delay clock after assertion of Hsync (Typical) */
  79#define EPPI_HDELAY             43
  80
  81/* FS2 (Vsync) Width    = FS1 (Hsync) Period * 10 */
  82#define EPPI_FS2W_LVB           (EPPI_LINE * 10)
  83
  84 /* FS2 (Vsync) Period   = FS1 (Hsync) Period * Lines per Frame */
  85#define EPPI_FS2P_LAVF          (EPPI_LINE * EPPI_FRAME)
  86
  87/* Vertical Delay after assertion of Vsync (2 Lines) */
  88#define EPPI_VDELAY             12
  89
  90#define EPPI_CLIP               0xFF00FF00
  91
  92/* EPPI Control register configuration value for RGB out
  93 * - EPPI as Output
  94 * GP 2 frame sync mode,
  95 * Internal Clock generation disabled, Internal FS generation enabled,
  96 * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
  97 * FS1 & FS2 are active high,
  98 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
  99 * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
 100 * Swapping Enabled,
 101 * One (DMA) Channel Mode,
 102 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
 103 * Regular watermark - when FIFO is 100% full,
 104 * Urgent watermark - when FIFO is 75% full
 105 */
 106
 107#define EPPI_CONTROL            (0x20136E2E)
 108
 109static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
 110{
 111        u32 sclk = get_sclk();
 112
 113        /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
 114
 115        return (((sclk / target_ppi_clk) / 2) - 1);
 116}
 117
 118void Init_PPI(void)
 119{
 120        u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
 121
 122        bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
 123        bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
 124        bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
 125        bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
 126        bfin_write_EPPI0_CLIP(EPPI_CLIP);
 127
 128        bfin_write_EPPI0_FRAME(EPPI_FRAME);
 129        bfin_write_EPPI0_LINE(EPPI_LINE);
 130
 131        bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
 132        bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
 133        bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
 134        bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
 135
 136        bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
 137
 138/*
 139 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
 140 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
 141 */
 142#if defined(CONFIG_VIDEO_RGB666)
 143        bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
 144                                 RGB_FMT_EN);
 145#else
 146        bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
 147                                 ~RGB_FMT_EN);
 148#endif
 149
 150}
 151
 152#define               DEB2_URGENT  0x2000       /* DEB2 Urgent */
 153
 154void Init_DMA(void *dst)
 155{
 156#if defined(CONFIG_DEB_DMA_URGENT)
 157        bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
 158#endif
 159
 160        bfin_write_DMA12_START_ADDR(dst);
 161
 162        /* X count */
 163        bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
 164        bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
 165
 166        /* Y count */
 167        bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
 168        bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
 169
 170        /* DMA Config */
 171        bfin_write_DMA12_CONFIG(
 172            WDSIZE_32 | /* 32 bit DMA */
 173            DMA2D |             /* 2D DMA */
 174            FLOW_AUTO           /* autobuffer mode */
 175        );
 176}
 177
 178void Init_Ports(void)
 179{
 180        const unsigned short pins[] = {
 181                P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
 182                P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
 183                P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
 184                P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
 185#if !defined(CONFIG_VIDEO_RGB666)
 186                P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
 187                P_PPI0_D23,
 188#endif
 189                P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
 190        };
 191        peripheral_request_list(pins, "lcd");
 192
 193        gpio_request(GPIO_PE3, "lcd-disp");
 194        gpio_direction_output(GPIO_PE3, 1);
 195}
 196
 197void EnableDMA(void)
 198{
 199        bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
 200}
 201
 202void DisableDMA(void)
 203{
 204        bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
 205}
 206
 207/* enable and disable PPI functions */
 208void EnablePPI(void)
 209{
 210        bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
 211}
 212
 213void DisablePPI(void)
 214{
 215        bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
 216}
 217
 218int video_init(void *dst)
 219{
 220        Init_Ports();
 221        Init_DMA(dst);
 222        EnableDMA();
 223        Init_PPI();
 224        EnablePPI();
 225
 226        return 0;
 227}
 228
 229void video_stop(void)
 230{
 231        DisablePPI();
 232        DisableDMA();
 233}
 234
 235static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
 236{
 237        if (dcache_status())
 238                blackfin_dcache_flush_range(logo->data,
 239                                            logo->data + logo->size);
 240
 241        bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
 242
 243        /* Setup destination start address */
 244        bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
 245                                      + (y * LCD_X_RES * LCD_PIXEL_SIZE));
 246        /* Setup destination xcount */
 247        bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
 248        /* Setup destination xmodify */
 249        bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
 250
 251        /* Setup destination ycount */
 252        bfin_write_MDMA_D0_Y_COUNT(logo->height);
 253        /* Setup destination ymodify */
 254        bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE +
 255                                    DMA_SIZE16);
 256
 257        /* Setup Source start address */
 258        bfin_write_MDMA_S0_START_ADDR(logo->data);
 259        /* Setup Source xcount */
 260        bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
 261        /* Setup Source xmodify */
 262        bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
 263
 264        /* Setup Source ycount */
 265        bfin_write_MDMA_S0_Y_COUNT(logo->height);
 266        /* Setup Source ymodify */
 267        bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
 268
 269        /* Enable source DMA */
 270        bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
 271        SSYNC();
 272        bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
 273
 274        while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN) ;
 275
 276        bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE
 277                                      | DMA_ERR);
 278        bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE
 279                                      | DMA_ERR);
 280
 281}
 282
 283void video_putc(const char c)
 284{
 285}
 286
 287void video_puts(const char *s)
 288{
 289}
 290
 291int drv_video_init(void)
 292{
 293        int error, devices = 1;
 294        struct stdio_dev videodev;
 295
 296        u8 *dst;
 297        u32 fbmem_size =
 298            LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
 299
 300        dst = malloc(fbmem_size);
 301
 302        if (dst == NULL) {
 303                printf("Failed to alloc FB memory\n");
 304                return -1;
 305        }
 306#ifdef EASYLOGO_ENABLE_GZIP
 307        unsigned char *data = EASYLOGO_DECOMP_BUFFER;
 308        unsigned long src_len = EASYLOGO_ENABLE_GZIP;
 309        if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
 310                puts("Failed to decompress logo\n");
 311                free(dst);
 312                return -1;
 313        }
 314        bfin_logo.data = data;
 315#endif
 316
 317        memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0],
 318               fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
 319
 320        dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
 321                    (LCD_X_RES - bfin_logo.width) / 2,
 322                    (LCD_Y_RES - bfin_logo.height) / 2);
 323
 324        video_init(dst);        /* Video initialization */
 325
 326        memset(&videodev, 0, sizeof(videodev));
 327
 328        strcpy(videodev.name, "video");
 329        videodev.ext = DEV_EXT_VIDEO;   /* Video extensions */
 330        videodev.flags = DEV_FLAGS_SYSTEM;      /* No Output */
 331        videodev.putc = video_putc;     /* 'putc' function */
 332        videodev.puts = video_puts;     /* 'puts' function */
 333
 334        error = stdio_register(&videodev);
 335
 336        return (error == 0) ? devices : error;
 337}
 338
 339#endif
 340