1/****************************************************************************** 2 * This source code is dual-licensed. You may use it under the terms of the 3 * GNU General Public License version 2, or under the license below. 4 * 5 * This source code has been made available to you by IBM on an AS-IS 6 * basis. Anyone receiving this source is licensed under IBM 7 * copyrights to use it in any way he or she deems fit, including 8 * copying it, modifying it, compiling it, and redistributing it either 9 * with or without modifications. No license under IBM patents or 10 * patent applications is to be implied by the copyright license. 11 * 12 * Any user of this software should understand that IBM cannot provide 13 * technical support for this software and will not be responsible for 14 * any consequences resulting from the use of this software. 15 * 16 * Any person who transfers this source code or any derivative work 17 * must include the IBM copyright notice, this paragraph, and the 18 * preceding two paragraphs in the transferred software. 19 * 20 * COPYRIGHT I B M CORPORATION 1995 21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 22 * 23 *****************************************************************************/ 24#include <config.h> 25#include <asm/ppc4xx.h> 26 27#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 28 29#include <ppc_asm.tmpl> 30#include <ppc_defs.h> 31 32#include <asm/cache.h> 33#include <asm/mmu.h> 34 35#define LI32(reg,val) \ 36 addis reg,0,val@h;\ 37 ori reg,reg,val@l 38 39#define WDCR_EBC(reg,val) \ 40 addi r4,0,reg;\ 41 mtdcr EBC0_CFGADDR,r4;\ 42 addis r4,0,val@h;\ 43 ori r4,r4,val@l;\ 44 mtdcr EBC0_CFGDATA,r4 45 46#define WDCR_SDRAM(reg,val) \ 47 addi r4,0,reg;\ 48 mtdcr SDRAM0_CFGADDR,r4;\ 49 addis r4,0,val@h;\ 50 ori r4,r4,val@l;\ 51 mtdcr SDRAM0_CFGDATA,r4 52 53/****************************************************************************** 54 * Function: ext_bus_cntlr_init 55 * 56 * Description: Configures EBC Controller and a few basic chip selects. 57 * 58 * CS0 is setup to get the Boot Flash out of the addresss range 59 * so that we may setup a stack. CS7 is setup so that we can 60 * access and reset the hardware watchdog. 61 * 62 * IMPORTANT: For pass1 this code must run from 63 * cache since you can not reliably change a peripheral banks 64 * timing register (pbxap) while running code from that bank. 65 * For ex., since we are running from ROM on bank 0, we can NOT 66 * execute the code that modifies bank 0 timings from ROM, so 67 * we run it from cache. 68 * 69 * Notes: Does NOT use the stack. 70 *****************************************************************************/ 71 .section ".text" 72 .align 2 73 .globl ext_bus_cntlr_init 74 .type ext_bus_cntlr_init, @function 75ext_bus_cntlr_init: 76 mflr r0 77 /******************************************************************** 78 * Prefetch entire ext_bus_cntrl_init function into the icache. 79 * This is necessary because we are going to change the same CS we 80 * are executing from. Otherwise a CPU lockup may occur. 81 *******************************************************************/ 82 bl ..getAddr 83..getAddr: 84 mflr r3 /* get address of ..getAddr */ 85 86 /* Calculate number of cache lines for this function */ 87 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) 88 mtctr r4 89..ebcloop: 90 icbt r0, r3 /* prefetch cache line for addr in r3*/ 91 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ 92 bdnz ..ebcloop /* continue for $CTR cache lines */ 93 94 /******************************************************************** 95 * Delay to ensure all accesses to ROM are complete before changing 96 * bank 0 timings. 200usec should be enough. 97 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. 98 *******************************************************************/ 99 addis r3, 0, 0x0 100 ori r3, r3, 0xA000 /* wait 200us from reset */ 101 mtctr r3 102..spinlp: 103 bdnz ..spinlp /* spin loop */ 104 105 /******************************************************************** 106 * SETUP CPC0_CR0 107 *******************************************************************/ 108 LI32(r4, 0x007000c0) 109 mtdcr CPC0_CR0, r4 110 111 /******************************************************************** 112 * Setup CPC0_CR1: Change PCIINT signal to PerWE 113 *******************************************************************/ 114 mfdcr r4, CPC0_CR1 115 ori r4, r4, 0x4000 116 mtdcr CPC0_CR1, r4 117 118 /******************************************************************** 119 * Setup External Bus Controller (EBC). 120 *******************************************************************/ 121 WDCR_EBC(EBC0_CFG, 0xd84c0000) 122 /******************************************************************** 123 * Memory Bank 0 (Intel 28F128J3 Flash) initialization 124 *******************************************************************/ 125 /*WDCR_EBC(PB1AP, 0x02869200)*/ 126 WDCR_EBC(PB1AP, 0x07869200) 127 WDCR_EBC(PB0CR, 0xfe0bc000) 128 /******************************************************************** 129 * Memory Bank 1 (Holtek HT6542B PS/2) initialization 130 *******************************************************************/ 131 WDCR_EBC(PB1AP, 0x1f869200) 132 WDCR_EBC(PB1CR, 0xf0818000) 133 /******************************************************************** 134 * Memory Bank 2 (Epson S1D13506) initialization 135 *******************************************************************/ 136 WDCR_EBC(PB2AP, 0x05860300) 137 WDCR_EBC(PB2CR, 0xf045a000) 138 /******************************************************************** 139 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization 140 *******************************************************************/ 141 WDCR_EBC(PB3AP, 0x0387d200) 142 WDCR_EBC(PB3CR, 0xf021c000) 143 /******************************************************************** 144 * Memory Bank 4-7 (Unused) initialization 145 *******************************************************************/ 146 WDCR_EBC(PB4AP, 0) 147 WDCR_EBC(PB4CR, 0) 148 WDCR_EBC(PB5AP, 0) 149 WDCR_EBC(PB5CR, 0) 150 WDCR_EBC(PB6AP, 0) 151 WDCR_EBC(PB6CR, 0) 152 WDCR_EBC(PB7AP, 0) 153 WDCR_EBC(PB7CR, 0) 154 155 /* We are all done */ 156 mtlr r0 /* Restore link register */ 157 blr /* Return to calling function */ 158.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init 159/* end ext_bus_cntlr_init() */ 160 161/****************************************************************************** 162 * Function: sdram_init 163 * 164 * Description: Configures SDRAM memory banks. 165 * 166 * Notes: Does NOT use the stack. 167 *****************************************************************************/ 168 .section ".text" 169 .align 2 170 .globl sdram_init 171 .type sdram_init, @function 172sdram_init: 173 174 /* 175 * Disable memory controller to allow 176 * values to be changed. 177 */ 178 WDCR_SDRAM(SDRAM0_CFG, 0x00000000) 179 180 /* 181 * Configure Memory Banks 182 */ 183 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) 184 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) 185 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) 186 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) 187 188 /* 189 * Set up SDTR1 (SDRAM Timing Register) 190 */ 191 WDCR_SDRAM(SDRAM0_TR, 0x00854009) 192 193 /* 194 * Set RTR (Refresh Timing Register) 195 */ 196 WDCR_SDRAM(SDRAM0_RTR, 0x10000000) 197 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ 198 199 /******************************************************************** 200 * Delay to ensure 200usec have elapsed since reset. Assume worst 201 * case that the core is running 200Mhz: 202 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 203 *******************************************************************/ 204 addis r3, 0, 0x0000 205 ori r3, r3, 0xA000 /* Wait >200us from reset */ 206 mtctr r3 207..spinlp2: 208 bdnz ..spinlp2 /* spin loop */ 209 210 /******************************************************************** 211 * Set memory controller options reg, MCOPT1. 212 *******************************************************************/ 213 WDCR_SDRAM(SDRAM0_CFG,0x80800000) 214 215..sdri_done: 216 blr /* Return to calling function */ 217.Lfe1: .size sdram_init,.Lfe1-sdram_init 218/* end sdram_init() */ 219