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26#include <common.h>
27#include <hwconfig.h>
28#include <i2c.h>
29#include <libfdt.h>
30#include <fdt_support.h>
31#include <pci.h>
32#include <mpc83xx.h>
33#include <netdev.h>
34#include <asm/io.h>
35#include <ns16550.h>
36#include <nand.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
40int board_early_init_f(void)
41{
42 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
43
44 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
45 gd->flags |= GD_FLG_SILENT;
46
47 return 0;
48}
49
50#ifndef CONFIG_NAND_SPL
51
52static u8 read_board_info(void)
53{
54 u8 val8;
55 i2c_set_bus_num(0);
56
57 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
58 return val8;
59 else
60 return 0;
61}
62
63int checkboard(void)
64{
65 static const char * const rev_str[] = {
66 "0.0",
67 "0.1",
68 "1.0",
69 "1.1",
70 "<unknown>",
71 };
72 u8 info;
73 int i;
74
75 info = read_board_info();
76 i = (!info) ? 4: info & 0x03;
77
78 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
79
80 return 0;
81}
82
83static struct pci_region pci_regions[] = {
84 {
85 bus_start: CONFIG_SYS_PCI_MEM_BASE,
86 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
87 size: CONFIG_SYS_PCI_MEM_SIZE,
88 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
89 },
90 {
91 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
92 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
93 size: CONFIG_SYS_PCI_MMIO_SIZE,
94 flags: PCI_REGION_MEM
95 },
96 {
97 bus_start: CONFIG_SYS_PCI_IO_BASE,
98 phys_start: CONFIG_SYS_PCI_IO_PHYS,
99 size: CONFIG_SYS_PCI_IO_SIZE,
100 flags: PCI_REGION_IO
101 }
102};
103
104static struct pci_region pcie_regions_0[] = {
105 {
106 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
107 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
108 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
109 .flags = PCI_REGION_MEM,
110 },
111 {
112 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
113 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
114 .size = CONFIG_SYS_PCIE1_IO_SIZE,
115 .flags = PCI_REGION_IO,
116 },
117};
118
119static struct pci_region pcie_regions_1[] = {
120 {
121 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
122 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
123 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
124 .flags = PCI_REGION_MEM,
125 },
126 {
127 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
128 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
129 .size = CONFIG_SYS_PCIE2_IO_SIZE,
130 .flags = PCI_REGION_IO,
131 },
132};
133
134void pci_init_board(void)
135{
136 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
137 volatile sysconf83xx_t *sysconf = &immr->sysconf;
138 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
139 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
140 volatile law83xx_t *pcie_law = sysconf->pcielaw;
141 struct pci_region *reg[] = { pci_regions };
142 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
143
144
145 clk->occr |= 0xe0000000;
146
147
148
149
150 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
151 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
152
153 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
154 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
155
156 mpc83xx_pci_init(1, reg);
157
158
159 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
160 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
161
162
163 out_be32(&sysconf->pecr1, 0xE0008000);
164 out_be32(&sysconf->pecr2, 0xE0008000);
165 udelay(2000);
166
167
168 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
169 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
170
171 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
172 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
173
174 mpc83xx_pcie_init(2, pcie_reg);
175}
176
177#if defined(CONFIG_OF_BOARD_SETUP)
178void fdt_tsec1_fixup(void *fdt, bd_t *bd)
179{
180 const char disabled[] = "disabled";
181 const char *path;
182 int ret;
183
184 if (hwconfig_arg_cmp("board_type", "tsec1")) {
185 return;
186 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
187 printf("NOTICE: No or unknown board_type hwconfig specified.\n"
188 " Assuming board with TSEC1.\n");
189 return;
190 }
191
192 ret = fdt_path_offset(fdt, "/aliases");
193 if (ret < 0) {
194 printf("WARNING: can't find /aliases node\n");
195 return;
196 }
197
198 path = fdt_getprop(fdt, ret, "ethernet0", NULL);
199 if (!path) {
200 printf("WARNING: can't find ethernet0 alias\n");
201 return;
202 }
203
204 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
205}
206
207void ft_board_setup(void *blob, bd_t *bd)
208{
209 ft_cpu_setup(blob, bd);
210#ifdef CONFIG_PCI
211 ft_pci_setup(blob, bd);
212#endif
213 fdt_fixup_dr_usb(blob, bd);
214 fdt_tsec1_fixup(blob, bd);
215}
216#endif
217
218int board_eth_init(bd_t *bis)
219{
220 cpu_eth_init(bis);
221 return pci_eth_init(bis);
222}
223
224#else
225
226int checkboard(void)
227{
228 puts("Board: Freescale MPC8315ERDB\n");
229 return 0;
230}
231
232void board_init_f(ulong bootflag)
233{
234 board_early_init_f();
235 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
236 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
237 puts("NAND boot... ");
238 init_timebase();
239 initdram(0);
240 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
241 CONFIG_SYS_NAND_U_BOOT_RELOC);
242}
243
244void board_init_r(gd_t *gd, ulong dest_addr)
245{
246 nand_boot();
247}
248
249void putc(char c)
250{
251 if (gd->flags & GD_FLG_SILENT)
252 return;
253
254 if (c == '\n')
255 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
256
257 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
258}
259
260#endif
261
