LXR uboot/board/freescale/mpc8349itx/pci.c

   1/*
   2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <common.h>
  24
  25#include <asm/mmu.h>
  26#include <asm/io.h>
  27#include <mpc83xx.h>
  28#include <pci.h>
  29#include <i2c.h>
  30#include <asm/fsl_i2c.h>
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34static struct pci_region pci1_regions[] = {
  35        {
  36                bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  37                phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  38                size: CONFIG_SYS_PCI1_MEM_SIZE,
  39                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  40        },
  41        {
  42                bus_start: CONFIG_SYS_PCI1_IO_BASE,
  43                phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  44                size: CONFIG_SYS_PCI1_IO_SIZE,
  45                flags: PCI_REGION_IO
  46        },
  47        {
  48                bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  49                phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  50                size: CONFIG_SYS_PCI1_MMIO_SIZE,
  51                flags: PCI_REGION_MEM
  52        },
  53};
  54
  55#ifdef CONFIG_MPC83XX_PCI2
  56static struct pci_region pci2_regions[] = {
  57        {
  58                bus_start: CONFIG_SYS_PCI2_MEM_BASE,
  59                phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
  60                size: CONFIG_SYS_PCI2_MEM_SIZE,
  61                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  62        },
  63        {
  64                bus_start: CONFIG_SYS_PCI2_IO_BASE,
  65                phys_start: CONFIG_SYS_PCI2_IO_PHYS,
  66                size: CONFIG_SYS_PCI2_IO_SIZE,
  67                flags: PCI_REGION_IO
  68        },
  69        {
  70                bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
  71                phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
  72                size: CONFIG_SYS_PCI2_MMIO_SIZE,
  73                flags: PCI_REGION_MEM
  74        },
  75};
  76#endif
  77
  78void pci_init_board(void)
  79{
  80        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  81        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  82        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  83#ifndef CONFIG_MPC83XX_PCI2
  84        struct pci_region *reg[] = { pci1_regions };
  85#else
  86        struct pci_region *reg[] = { pci1_regions, pci2_regions };
  87#endif
  88        u8 reg8;
  89
  90#ifdef CONFIG_HARD_I2C
  91        i2c_set_bus_num(1);
  92        /* Read the PCI_M66EN jumper setting */
  93        if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
  94            (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
  95                if (reg8 & I2C_8574_PCI66)
  96                        clk->occr = 0xff000000; /* 66 MHz PCI */
  97                else
  98                        clk->occr = 0xff600001; /* 33 MHz PCI */
  99        } else {
 100                clk->occr = 0xff600001; /* 33 MHz PCI */
 101        }
 102#else
 103        clk->occr = 0xff000000; /* 66 MHz PCI */
 104#endif
 105        udelay(2000);
 106
 107        /* Configure PCI Local Access Windows */
 108        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 109        pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 110
 111        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 112        pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
 113
 114        udelay(2000);
 115
 116#ifndef CONFIG_MPC83XX_PCI2
 117        mpc83xx_pci_init(1, reg);
 118#else
 119        mpc83xx_pci_init(2, reg);
 120#endif
 121}
 122