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23#include <common.h>
24#include <command.h>
25#include <asm/processor.h>
26#include <asm/mmu.h>
27#include <asm/cache.h>
28#include <asm/immap_85xx.h>
29#include <asm/fsl_serdes.h>
30#include <asm/io.h>
31#include <miiphy.h>
32#include <libfdt.h>
33#include <fdt_support.h>
34#include <fsl_mdio.h>
35#include <tsec.h>
36#include <vsc7385.h>
37#include <netdev.h>
38#include <rtc.h>
39#include <i2c.h>
40#include <hwconfig.h>
41
42DECLARE_GLOBAL_DATA_PTR;
43
44#define VSC7385_RST_SET 0x00080000
45#define SLIC_RST_SET 0x00040000
46#define SGMII_PHY_RST_SET 0x00020000
47#define PCIE_RST_SET 0x00010000
48#define RGMII_PHY_RST_SET 0x02000000
49
50#define USB_RST_CLR 0x04000000
51#define USB2_PORT_OUT_EN 0x01000000
52
53#define GPIO_DIR 0x060f0000
54
55#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
56 SGMII_PHY_RST_SET | PCIE_RST_SET | \
57 RGMII_PHY_RST_SET
58
59#define SYSCLK_MASK 0x00200000
60#define BOARDREV_MASK 0x10100000
61#define BOARDREV_C 0x00100000
62#define BOARDREV_D 0x00000000
63
64#define SYSCLK_66 66666666
65#define SYSCLK_100 100000000
66
67unsigned long get_board_sys_clk(ulong dummy)
68{
69 volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
70 u32 val_gpdat, sysclk_gpio;
71
72 val_gpdat = in_be32(&pgpio->gpdat);
73 sysclk_gpio = val_gpdat & SYSCLK_MASK;
74
75 if(sysclk_gpio == 0)
76 return SYSCLK_66;
77 else
78 return SYSCLK_100;
79
80 return 0;
81}
82
83#ifdef CONFIG_MMC
84int board_early_init_f (void)
85{
86 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
87
88 setbits_be32(&gur->pmuxcr,
89 (MPC85xx_PMUXCR_SDHC_CD |
90 MPC85xx_PMUXCR_SDHC_WP));
91 return 0;
92}
93#endif
94
95int checkboard (void)
96{
97 u32 val_gpdat, board_rev_gpio;
98 volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
99 char board_rev = 0;
100 struct cpu_type *cpu;
101
102 val_gpdat = in_be32(&pgpio->gpdat);
103 board_rev_gpio = val_gpdat & BOARDREV_MASK;
104 if (board_rev_gpio == BOARDREV_C)
105 board_rev = 'C';
106 else if (board_rev_gpio == BOARDREV_D)
107 board_rev = 'D';
108 else
109 panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
110
111 cpu = gd->cpu;
112 printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
113#ifdef CONFIG_PHYS_64BIT
114 puts ("(36-bit addrmap) \n");
115#endif
116 setbits_be32(&pgpio->gpdir, GPIO_DIR);
117
118
119
120
121
122
123
124
125
126
127
128 clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
129
130 return 0;
131}
132
133int misc_init_r(void)
134{
135#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
136 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
137 ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
138
139 setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
140 setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
141 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
142#endif
143 return 0;
144}
145
146int board_early_init_r(void)
147{
148 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
149 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
150 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
151 unsigned int orig_bus = i2c_get_bus_num();
152 u8 i2c_data;
153
154 i2c_set_bus_num(1);
155 if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
156 1, &i2c_data, sizeof(i2c_data)) == 0) {
157 if (i2c_data & 0x2)
158 puts("NOR Flash Bank : Secondary\n");
159 else
160 puts("NOR Flash Bank : Primary\n");
161
162 if (i2c_data & 0x1) {
163 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
164 puts("SD/MMC : 8-bit Mode\n");
165 puts("eSPI : Disabled\n");
166 } else {
167 puts("SD/MMC : 4-bit Mode\n");
168 puts("eSPI : Enabled\n");
169 }
170 } else {
171 puts("Failed reading I2C Chip 0x18 on bus 1\n");
172 }
173 i2c_set_bus_num(orig_bus);
174
175
176
177
178
179
180
181 flush_dcache();
182 invalidate_icache();
183
184
185 disable_tlb(flash_esel);
186
187 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
188 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
189 0, flash_esel, BOOKE_PAGESZ_16M, 1);
190 rtc_reset();
191 return 0;
192}
193
194
195#ifdef CONFIG_TSEC_ENET
196int board_eth_init(bd_t *bis)
197{
198 struct fsl_pq_mdio_info mdio_info;
199 struct tsec_info_struct tsec_info[4];
200 int num = 0;
201 char *tmp;
202 unsigned int vscfw_addr;
203
204#ifdef CONFIG_TSEC1
205 SET_STD_TSEC_INFO(tsec_info[num], 1);
206 num++;
207#endif
208#ifdef CONFIG_TSEC2
209 SET_STD_TSEC_INFO(tsec_info[num], 2);
210 num++;
211#endif
212#ifdef CONFIG_TSEC3
213 SET_STD_TSEC_INFO(tsec_info[num], 3);
214 if (is_serdes_configured(SGMII_TSEC3)) {
215 puts("eTSEC3 is in sgmii mode.\n");
216 tsec_info[num].flags |= TSEC_SGMII;
217 }
218 num++;
219#endif
220 if (!num) {
221 printf("No TSECs initialized\n");
222 return 0;
223 }
224#ifdef CONFIG_VSC7385_ENET
225
226 if ((tmp = getenv ("vscfw_addr")) != NULL) {
227 vscfw_addr = simple_strtoul (tmp, NULL, 16);
228 printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
229 if (vsc7385_upload_firmware((void *) vscfw_addr,
230 CONFIG_VSC7385_IMAGE_SIZE))
231 puts("Failure uploading VSC7385 microcode.\n");
232 } else
233 puts("No address specified for VSC7385 microcode.\n");
234#endif
235
236 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
237 mdio_info.name = DEFAULT_MII_NAME;
238 fsl_pq_mdio_init(bis, &mdio_info);
239
240 tsec_eth_init(bis, tsec_info, num);
241
242 return pci_eth_init(bis);
243}
244#endif
245
246#if defined(CONFIG_OF_BOARD_SETUP)
247extern void ft_pci_board_setup(void *blob);
248
249void ft_board_setup(void *blob, bd_t *bd)
250{
251 const char *soc_usb_compat = "fsl-usb2-dr";
252 int err, usb1_off, usb2_off;
253 phys_addr_t base;
254 phys_size_t size;
255
256 ft_cpu_setup(blob, bd);
257
258 base = getenv_bootm_low();
259 size = getenv_bootm_size();
260
261#if defined(CONFIG_PCI)
262 ft_pci_board_setup(blob);
263#endif
264
265 fdt_fixup_memory(blob, (u64)base, (u64)size);
266
267#if defined(CONFIG_HAS_FSL_DR_USB)
268 fdt_fixup_dr_usb(blob, bd);
269#endif
270
271#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
272
273 if (hwconfig("usb2")) {
274 const char *soc_elbc_compat = "fsl,p1020-elbc";
275 int off = fdt_node_offset_by_compatible(blob, -1,
276 soc_elbc_compat);
277 if (off < 0) {
278 printf("WARNING: could not find compatible node"
279 " %s: %s.\n", soc_elbc_compat,
280 fdt_strerror(off));
281 return;
282 }
283 err = fdt_del_node(blob, off);
284 if (err < 0) {
285 printf("WARNING: could not remove %s: %s.\n",
286 soc_elbc_compat, fdt_strerror(err));
287 }
288 return;
289 }
290#endif
291
292 usb1_off = fdt_node_offset_by_compatible(blob, -1,
293 soc_usb_compat);
294 if (usb1_off < 0) {
295 printf("WARNING: could not find compatible node"
296 " %s: %s.\n", soc_usb_compat,
297 fdt_strerror(usb1_off));
298 return;
299 }
300 usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
301 soc_usb_compat);
302 if (usb2_off < 0) {
303 printf("WARNING: could not find compatible node"
304 " %s: %s.\n", soc_usb_compat,
305 fdt_strerror(usb2_off));
306 return;
307 }
308 err = fdt_del_node(blob, usb2_off);
309 if (err < 0)
310 printf("WARNING: could not remove %s: %s.\n",
311 soc_usb_compat, fdt_strerror(err));
312}
313#endif
314
