LXR uboot/board/kup/kup4x/kup4x.c

   1/*
   2 * (C) Copyright 2000-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <mpc8xx.h>
  27#include <post.h>
  28#include "../common/kup.h"
  29#include <asm/io.h>
  30
  31
  32#define _NOT_USED_      0xFFFFFFFF
  33
  34const uint sdram_table[] = {
  35        /*
  36         * Single Read. (Offset 0 in UPMA RAM)
  37         */
  38        0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  39        0x1FF77C47,             /* last */
  40
  41        /*
  42         * SDRAM Initialization (offset 5 in UPMA RAM)
  43         *
  44         * This is no UPM entry point. The following definition uses
  45         * the remaining space to establish an initialization
  46         * sequence, which is executed by a RUN command.
  47         *
  48         */
  49        0x1FF77C35, 0xEFEABC34, 0x1FB57C35,     /* last */
  50
  51        /*
  52         * Burst Read. (Offset 8 in UPMA RAM)
  53         */
  54        0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  55        0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  56        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  57        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  58
  59        /*
  60         * Single Write. (Offset 18 in UPMA RAM)
  61         */
  62        0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  63        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  64
  65        /*
  66         * Burst Write. (Offset 20 in UPMA RAM)
  67         */
  68        0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  69        0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47,     /* last */
  70        _NOT_USED_,
  71        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  72        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73
  74        /*
  75         * Refresh  (Offset 30 in UPMA RAM)
  76         */
  77        0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  78        0xFFFFFC84, 0xFFFFFC07, /* last */
  79        _NOT_USED_, _NOT_USED_,
  80        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  81
  82        /*
  83         * Exception. (Offset 3c in UPMA RAM)
  84         */
  85        0x7FFFFC07,             /* last */
  86        _NOT_USED_, _NOT_USED_, _NOT_USED_,
  87};
  88
  89
  90/*
  91 * Check Board Identity:
  92 */
  93
  94int checkboard(void)
  95{
  96        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  97        volatile memctl8xx_t *memctl = &immap->im_memctl;
  98        uchar latch, rev, mod;
  99
 100        /*
 101         * Init ChipSelect #4 (CAN + HW-Latch)
 102         */
 103        out_be32(&memctl->memc_or4, 0xFFFF8926);
 104        out_be32(&memctl->memc_br4, 0x90000401);
 105
 106        latch = in_8( (unsigned char *) LATCH_ADDR);
 107        rev = (latch & 0xF8) >> 3;
 108        mod = (latch & 0x03);
 109
 110        printf("Board: KUP4X Rev %d.%d\n", rev, mod);
 111
 112        return 0;
 113}
 114
 115
 116phys_size_t initdram(int board_type)
 117{
 118        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 119        volatile memctl8xx_t *memctl = &immap->im_memctl;
 120
 121        upmconfig(UPMA, (uint *) sdram_table,
 122                   sizeof (sdram_table) / sizeof (uint));
 123
 124        out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 125
 126        out_be32(&memctl->memc_mar, 0x00000088);
 127
 128        out_be32(&memctl->memc_mamr,
 129                 CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */
 130
 131        udelay(200);
 132
 133        /* perform SDRAM initializsation sequence */
 134
 135        /* SDRAM bank 0 */
 136        out_be32(&memctl->memc_mcr, 0x80002105);
 137        udelay(1);
 138        out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
 139        udelay(1);
 140        out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
 141        udelay(1);
 142
 143        /* SDRAM bank 1 */
 144        out_be32(&memctl->memc_mcr, 0x80004105);
 145        udelay(1);
 146        out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
 147        udelay(1);
 148        out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
 149        udelay(1);
 150
 151        /* SDRAM bank 2 */
 152        out_be32(&memctl->memc_mcr, 0x80006105);
 153        udelay(1);
 154        out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
 155        udelay(1);
 156        out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
 157        udelay(1);
 158
 159        /* SDRAM bank 3 */
 160        out_be32(&memctl->memc_mcr, 0x8000C105);
 161        udelay(1);
 162        out_be32(&memctl->memc_mcr, 0x8000C830); /* execute twice */
 163        udelay(1);
 164        out_be32(&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */
 165        udelay(1);
 166
 167        setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
 168
 169        udelay(1000);
 170        /* 4 x 16 MB */
 171        out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
 172        udelay(1000);
 173        out_be32(&memctl->memc_or1, 0xFF000A00);
 174        out_be32(&memctl->memc_br1, 0x00000081);
 175        out_be32(&memctl->memc_or2, 0xFE000A00);
 176        out_be32(&memctl->memc_br2, 0x01000081);
 177        out_be32(&memctl->memc_or3, 0xFD000A00);
 178        out_be32(&memctl->memc_br3, 0x02000081);
 179        out_be32(&memctl->memc_or6, 0xFC000A00);
 180        out_be32(&memctl->memc_br6, 0x03000081);
 181        udelay(10000);
 182
 183        return (4 * 16 * 1024 * 1024);
 184}
 185
 186int misc_init_r(void)
 187{
 188        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 189
 190#ifdef CONFIG_IDE_LED
 191        /* Configure PA8 as output port */
 192        setbits_be16(&immap->im_ioport.iop_padir, PA_8);
 193        setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
 194        clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
 195        setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
 196#endif
 197        load_sernum_ethaddr();
 198        setenv("hw", "4x");
 199        poweron_key();
 200        return 0;
 201}
 202