LXR uboot/board/netta2/netta2.c

   1/*
   2 * (C) Copyright 2000-2004
   3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25/*
  26 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  27 * U-Boot port on NetTA4 board
  28 */
  29
  30#include <common.h>
  31#include <miiphy.h>
  32
  33#include "mpc8xx.h"
  34
  35#ifdef CONFIG_HW_WATCHDOG
  36#include <watchdog.h>
  37#endif
  38
  39int fec8xx_miiphy_read(char *devname, unsigned char addr,
  40                unsigned char  reg, unsigned short *value);
  41int fec8xx_miiphy_write(char *devname, unsigned char  addr,
  42                unsigned char  reg, unsigned short value);
  43
  44/****************************************************************/
  45
  46/* some sane bit macros */
  47#define _BD(_b)                         (1U << (31-(_b)))
  48#define _BDR(_l, _h)                    (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  49
  50#define _BW(_b)                         (1U << (15-(_b)))
  51#define _BWR(_l, _h)                    (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  52
  53#define _BB(_b)                         (1U << (7-(_b)))
  54#define _BBR(_l, _h)                    (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  55
  56#define _B(_b)                          _BD(_b)
  57#define _BR(_l, _h)                     _BDR(_l, _h)
  58
  59/****************************************************************/
  60
  61/*
  62 * Check Board Identity:
  63 *
  64 * Return 1 always.
  65 */
  66
  67int checkboard(void)
  68{
  69        printf ("Intracom NetTA2 V%d\n", CONFIG_NETTA2_VERSION);
  70        return (0);
  71}
  72
  73/****************************************************************/
  74
  75#define _NOT_USED_      0xFFFFFFFF
  76
  77/****************************************************************/
  78
  79#define CS_0000         0x00000000
  80#define CS_0001         0x10000000
  81#define CS_0010         0x20000000
  82#define CS_0011         0x30000000
  83#define CS_0100         0x40000000
  84#define CS_0101         0x50000000
  85#define CS_0110         0x60000000
  86#define CS_0111         0x70000000
  87#define CS_1000         0x80000000
  88#define CS_1001         0x90000000
  89#define CS_1010         0xA0000000
  90#define CS_1011         0xB0000000
  91#define CS_1100         0xC0000000
  92#define CS_1101         0xD0000000
  93#define CS_1110         0xE0000000
  94#define CS_1111         0xF0000000
  95
  96#define BS_0000         0x00000000
  97#define BS_0001         0x01000000
  98#define BS_0010         0x02000000
  99#define BS_0011         0x03000000
 100#define BS_0100         0x04000000
 101#define BS_0101         0x05000000
 102#define BS_0110         0x06000000
 103#define BS_0111         0x07000000
 104#define BS_1000         0x08000000
 105#define BS_1001         0x09000000
 106#define BS_1010         0x0A000000
 107#define BS_1011         0x0B000000
 108#define BS_1100         0x0C000000
 109#define BS_1101         0x0D000000
 110#define BS_1110         0x0E000000
 111#define BS_1111         0x0F000000
 112
 113#define GPL0_AAAA       0x00000000
 114#define GPL0_AAA0       0x00200000
 115#define GPL0_AAA1       0x00300000
 116#define GPL0_000A       0x00800000
 117#define GPL0_0000       0x00A00000
 118#define GPL0_0001       0x00B00000
 119#define GPL0_111A       0x00C00000
 120#define GPL0_1110       0x00E00000
 121#define GPL0_1111       0x00F00000
 122
 123#define GPL1_0000       0x00000000
 124#define GPL1_0001       0x00040000
 125#define GPL1_1110       0x00080000
 126#define GPL1_1111       0x000C0000
 127
 128#define GPL2_0000       0x00000000
 129#define GPL2_0001       0x00010000
 130#define GPL2_1110       0x00020000
 131#define GPL2_1111       0x00030000
 132
 133#define GPL3_0000       0x00000000
 134#define GPL3_0001       0x00004000
 135#define GPL3_1110       0x00008000
 136#define GPL3_1111       0x0000C000
 137
 138#define GPL4_0000       0x00000000
 139#define GPL4_0001       0x00001000
 140#define GPL4_1110       0x00002000
 141#define GPL4_1111       0x00003000
 142
 143#define GPL5_0000       0x00000000
 144#define GPL5_0001       0x00000400
 145#define GPL5_1110       0x00000800
 146#define GPL5_1111       0x00000C00
 147#define LOOP            0x00000080
 148
 149#define EXEN            0x00000040
 150
 151#define AMX_COL         0x00000000
 152#define AMX_ROW         0x00000020
 153#define AMX_MAR         0x00000030
 154
 155#define NA              0x00000008
 156
 157#define UTA             0x00000004
 158
 159#define TODT            0x00000002
 160
 161#define LAST            0x00000001
 162
 163#define A10_AAAA        GPL0_AAAA
 164#define A10_AAA0        GPL0_AAA0
 165#define A10_AAA1        GPL0_AAA1
 166#define A10_000A        GPL0_000A
 167#define A10_0000        GPL0_0000
 168#define A10_0001        GPL0_0001
 169#define A10_111A        GPL0_111A
 170#define A10_1110        GPL0_1110
 171#define A10_1111        GPL0_1111
 172
 173#define RAS_0000        GPL1_0000
 174#define RAS_0001        GPL1_0001
 175#define RAS_1110        GPL1_1110
 176#define RAS_1111        GPL1_1111
 177
 178#define CAS_0000        GPL2_0000
 179#define CAS_0001        GPL2_0001
 180#define CAS_1110        GPL2_1110
 181#define CAS_1111        GPL2_1111
 182
 183#define WE_0000         GPL3_0000
 184#define WE_0001         GPL3_0001
 185#define WE_1110         GPL3_1110
 186#define WE_1111         GPL3_1111
 187
 188/* #define CAS_LATENCY  3  */
 189#define CAS_LATENCY     2
 190
 191const uint sdram_table[0x40] = {
 192
 193#if CAS_LATENCY == 3
 194        /* RSS */
 195        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 196        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 197        CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 198        CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 199        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 200        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 201        _NOT_USED_, _NOT_USED_,
 202
 203        /* RBS */
 204        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 205        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 206        CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 207        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 208        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 209        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 210        CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
 211        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
 212        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 213        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 214
 215        /* WSS */
 216        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 217        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 218        CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 219        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 220        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 221        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 222
 223        /* WBS */
 224        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 225        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 226        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
 227        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 228        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 229        CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 230        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 231        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 232        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 233        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 234        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 235#endif
 236
 237#if CAS_LATENCY == 2
 238        /* RSS */
 239        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 240        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 241        CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 242        CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 243        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 244        _NOT_USED_,
 245        _NOT_USED_, _NOT_USED_,
 246
 247        /* RBS */
 248        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 249        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 250        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 251        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 252        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 253        CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 254        CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 255        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 256        _NOT_USED_,
 257        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 258        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 259
 260        /* WSS */
 261        CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 262        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 263        CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 264        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 265        _NOT_USED_,
 266        _NOT_USED_, _NOT_USED_,
 267        _NOT_USED_,
 268
 269        /* WBS */
 270        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 271        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 272        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
 273        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 274        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 275        CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
 276        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 277        _NOT_USED_,
 278        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 279        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 280        _NOT_USED_, _NOT_USED_,
 281
 282#endif
 283
 284        /* UPT */
 285        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
 286        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 287        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 288        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 289        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
 290        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 291        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 292        _NOT_USED_, _NOT_USED_,
 293
 294        /* EXC */
 295        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
 296        _NOT_USED_,
 297
 298        /* REG */
 299        CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
 300        CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
 301};
 302
 303#if CONFIG_NETTA2_VERSION == 2
 304static const uint nandcs_table[0x40] = {
 305        /* RSS */
 306        CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
 307        CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
 308        CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
 309        CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
 310        CS_0000 | GPL4_0000 | GPL5_1111,
 311        CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
 312        CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
 313        CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,   /* NOP   */
 314
 315        /* RBS */
 316        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 317        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 318        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 319        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 320
 321        /* WSS */
 322        CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
 323        CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 324        CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 325        CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
 326        CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
 327        CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
 328        CS_0000 | GPL4_1111 | GPL5_1111,
 329        CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
 330
 331        /* WBS */
 332        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 333        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 334        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 335        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 336
 337        /* UPT */
 338        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 339        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 340        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 341
 342        /* EXC */
 343        CS_0001 | LAST,
 344        _NOT_USED_,
 345
 346        /* REG */
 347        CS_1110 ,
 348        CS_0001 | LAST,
 349};
 350#endif
 351
 352/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 353/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
 354#define MAR_SDRAM_INIT          ((CAS_LATENCY << 6) | 0x00000008LU)
 355
 356/* 8 */
 357#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 358                         MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 359                         MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 360
 361void check_ram(unsigned int addr, unsigned int size)
 362{
 363        unsigned int i, j, v, vv;
 364        volatile unsigned int *p;
 365        unsigned int pv;
 366
 367        p = (unsigned int *)addr;
 368        pv = (unsigned int)p;
 369        for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
 370                *p++ = pv;
 371
 372        p = (unsigned int *)addr;
 373        for (i = 0; i < size / sizeof(unsigned int); i++) {
 374                v = (unsigned int)p;
 375                vv = *p;
 376                if (vv != v) {
 377                        printf("%p: read %08x instead of %08x\n", p, vv, v);
 378                        hang();
 379                }
 380                p++;
 381        }
 382
 383        for (j = 0; j < 5; j++) {
 384                switch (j) {
 385                        case 0: v = 0x00000000; break;
 386                        case 1: v = 0xffffffff; break;
 387                        case 2: v = 0x55555555; break;
 388                        case 3: v = 0xaaaaaaaa; break;
 389                        default:v = 0xdeadbeef; break;
 390                }
 391                p = (unsigned int *)addr;
 392                for (i = 0; i < size / sizeof(unsigned int); i++) {
 393                        *p = v;
 394                        vv = *p;
 395                        if (vv != v) {
 396                                printf("%p: read %08x instead of %08x\n", p, vv, v);
 397                                hang();
 398                        }
 399                        *p = ~v;
 400                        p++;
 401                }
 402        }
 403}
 404
 405phys_size_t initdram(int board_type)
 406{
 407        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 408        volatile memctl8xx_t *memctl = &immap->im_memctl;
 409        long int size;
 410
 411        upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
 412
 413        /*
 414         * Preliminary prescaler for refresh
 415         */
 416        memctl->memc_mptpr = MPTPR_PTP_DIV8;
 417
 418        memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
 419
 420        /*
 421         * Map controller bank 3 to the SDRAM bank at preliminary address.
 422         */
 423        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 424        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 425
 426        memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
 427
 428        udelay(200);
 429
 430        /* perform SDRAM initialisation sequence */
 431        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
 432        udelay(1);
 433
 434        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
 435        udelay(1);
 436
 437        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
 438        udelay(1);
 439
 440        memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
 441
 442        udelay(10000);
 443
 444        {
 445                u32 d1, d2;
 446
 447                d1 = 0xAA55AA55;
 448                *(volatile u32 *)0 = d1;
 449                d2 = *(volatile u32 *)0;
 450                if (d1 != d2) {
 451                        printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 452                        hang();
 453                }
 454
 455                d1 = 0x55AA55AA;
 456                *(volatile u32 *)0 = d1;
 457                d2 = *(volatile u32 *)0;
 458                if (d1 != d2) {
 459                        printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 460                        hang();
 461                }
 462        }
 463
 464        size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
 465
 466        if (size == 0) {
 467                printf("SIZE is zero: LOOP on 0\n");
 468                for (;;) {
 469                        *(volatile u32 *)0 = 0;
 470                        (void)*(volatile u32 *)0;
 471                }
 472        }
 473
 474        return size;
 475}
 476
 477/* ------------------------------------------------------------------------- */
 478
 479void reset_phys(void)
 480{
 481        int phyno;
 482        unsigned short v;
 483
 484        udelay(10000);
 485        /* reset the damn phys */
 486        mii_init();
 487
 488        for (phyno = 0; phyno < 32; ++phyno) {
 489                fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
 490                if (v == 0xFFFF)
 491                        continue;
 492                fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
 493                udelay(10000);
 494                fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
 495                                BMCR_RESET | BMCR_ANENABLE);
 496                udelay(10000);
 497        }
 498}
 499
 500/* ------------------------------------------------------------------------- */
 501
 502/* GP = general purpose, SP = special purpose (on chip peripheral) */
 503
 504/* bits that can have a special purpose or can be configured as inputs/outputs */
 505#define PA_GP_INMASK    0
 506#define PA_GP_OUTMASK   (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
 507#define PA_SP_MASK      0
 508#define PA_ODR_VAL      0
 509#define PA_GP_OUTVAL    (_BW(3) | _BW(14) | _BW(15))
 510#define PA_SP_DIRVAL    0
 511
 512#define PB_GP_INMASK    _B(28)
 513#define PB_GP_OUTMASK   (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
 514#define PB_SP_MASK      (_BR(22, 25))
 515#define PB_ODR_VAL      0
 516#define PB_GP_OUTVAL    (_B(26) | _B(27) | _B(29) | _B(30))
 517#define PB_SP_DIRVAL    0
 518
 519#if CONFIG_NETTA2_VERSION == 1
 520#define PC_GP_INMASK    _BW(12)
 521#define PC_GP_OUTMASK   (_BW(10) | _BW(11) | _BW(13) | _BW(15))
 522#elif CONFIG_NETTA2_VERSION == 2
 523#define PC_GP_INMASK    (_BW(13) | _BW(15))
 524#define PC_GP_OUTMASK   (_BW(10) | _BW(11) | _BW(12))
 525#endif
 526#define PC_SP_MASK      0
 527#define PC_SOVAL        0
 528#define PC_INTVAL       0
 529#define PC_GP_OUTVAL    (_BW(10) | _BW(11))
 530#define PC_SP_DIRVAL    0
 531
 532#if CONFIG_NETTA2_VERSION == 1
 533#define PE_GP_INMASK    _B(31)
 534#define PE_GP_OUTMASK   (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
 535#define PE_GP_OUTVAL    (_B(20) | _B(24) | _B(27) | _B(28))
 536#elif CONFIG_NETTA2_VERSION == 2
 537#define PE_GP_INMASK    _BR(28, 31)
 538#define PE_GP_OUTMASK   (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
 539#define PE_GP_OUTVAL    (_B(20) | _B(24) | _B(27))
 540#endif
 541#define PE_SP_MASK      0
 542#define PE_ODR_VAL      0
 543#define PE_SP_DIRVAL    0
 544
 545int board_early_init_f(void)
 546{
 547        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 548        volatile iop8xx_t *ioport = &immap->im_ioport;
 549        volatile cpm8xx_t *cpm = &immap->im_cpm;
 550        volatile memctl8xx_t *memctl = &immap->im_memctl;
 551
 552        /* NAND chip select */
 553#if CONFIG_NETTA2_VERSION == 1
 554        memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
 555        memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 556#elif CONFIG_NETTA2_VERSION == 2
 557        upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
 558        memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
 559        memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
 560        memctl->memc_mamr = 0;  /* all clear */
 561#endif
 562
 563        /* DSP chip select */
 564        memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
 565        memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 566
 567#if CONFIG_NETTA2_VERSION == 1
 568        memctl->memc_br4 &= ~BR_V;
 569#endif
 570        memctl->memc_br5 &= ~BR_V;
 571        memctl->memc_br6 &= ~BR_V;
 572        memctl->memc_br7 &= ~BR_V;
 573
 574        ioport->iop_padat       = PA_GP_OUTVAL;
 575        ioport->iop_paodr       = PA_ODR_VAL;
 576        ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
 577        ioport->iop_papar       = PA_SP_MASK;
 578
 579        cpm->cp_pbdat           = PB_GP_OUTVAL;
 580        cpm->cp_pbodr           = PB_ODR_VAL;
 581        cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
 582        cpm->cp_pbpar           = PB_SP_MASK;
 583
 584        ioport->iop_pcdat       = PC_GP_OUTVAL;
 585        ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
 586        ioport->iop_pcso        = PC_SOVAL;
 587        ioport->iop_pcint       = PC_INTVAL;
 588        ioport->iop_pcpar       = PC_SP_MASK;
 589
 590        cpm->cp_pedat           = PE_GP_OUTVAL;
 591        cpm->cp_peodr           = PE_ODR_VAL;
 592        cpm->cp_pedir           = PE_GP_OUTMASK | PE_SP_DIRVAL;
 593        cpm->cp_pepar           = PE_SP_MASK;
 594
 595        return 0;
 596}
 597
 598#ifdef CONFIG_HW_WATCHDOG
 599
 600void hw_watchdog_reset(void)
 601{
 602        /* XXX add here the really funky stuff */
 603}
 604
 605#endif
 606
 607#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 608int overwrite_console(void)
 609{
 610        /* printf("overwrite_console called\n"); */
 611        return 0;
 612}
 613#endif
 614
 615extern int drv_phone_init(void);
 616extern int drv_phone_use_me(void);
 617extern int drv_phone_is_idle(void);
 618
 619int misc_init_r(void)
 620{
 621        return 0;
 622}
 623
 624int last_stage_init(void)
 625{
 626#if CONFIG_NETTA2_VERSION == 2
 627        int i;
 628#endif
 629
 630#if CONFIG_NETTA2_VERSION == 2
 631        /* assert peripheral reset */
 632        ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
 633        for (i = 0; i < 10; i++)
 634                udelay(1000);
 635        ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
 636#endif
 637        reset_phys();
 638
 639        return 0;
 640}
 641