LXR uboot/board/sheldon/simpc8313/simpc8313.c

   1/*
   2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
   3 * Copyright (C) Sheldon Instruments, Inc. 2008
   4 *
   5 * Author: Ron Madrid <info@sheldoninst.com>
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <common.h>
  27#include <libfdt.h>
  28#include <pci.h>
  29#include <mpc83xx.h>
  30#include <ns16550.h>
  31#include <nand.h>
  32#include <asm/io.h>
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36#ifndef CONFIG_NAND_SPL
  37int checkboard(void)
  38{
  39        puts("Board: Sheldon Instruments SIMPC8313\n");
  40        return 0;
  41}
  42
  43static struct pci_region pci_regions[] = {
  44        {
  45                bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  46                phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  47                size: CONFIG_SYS_PCI1_MEM_SIZE,
  48                flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  49        },
  50        {
  51                bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  52                phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  53                size: CONFIG_SYS_PCI1_MMIO_SIZE,
  54                flags: PCI_REGION_MEM
  55        },
  56        {
  57                bus_start: CONFIG_SYS_PCI1_IO_BASE,
  58                phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  59                size: CONFIG_SYS_PCI1_IO_SIZE,
  60                flags: PCI_REGION_IO
  61        }
  62};
  63
  64void pci_init_board(void)
  65{
  66        volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  67        volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  68        volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  69        struct pci_region *reg[] = { pci_regions };
  70
  71        /* Enable all 3 PCI_CLK_OUTPUTs. */
  72        clk->occr |= 0xe0000000;
  73
  74        /*
  75         * Configure PCI Local Access Windows
  76         */
  77        pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  78        pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  79
  80        pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  81        pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  82
  83        mpc83xx_pci_init(1, reg);
  84}
  85
  86/*
  87 * Miscellaneous late-boot configurations
  88 */
  89int misc_init_r(void)
  90{
  91        int rc = 0;
  92        immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  93        fsl_lbc_t *lbus = &immap->im_lbc;
  94        u32 *mxmr = &lbus->mamr;        /* Pointer to mamr */
  95
  96        /* UPM Table Configuration Code */
  97        static uint UPMATable[] = {
  98                /* Read Single-Beat (RSS) */
  99                0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
 100                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 101                /* Read Burst (RBS) */
 102                0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
 103                0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
 104                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 105                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 106                /* Write Single-Beat (WSS) */
 107                0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
 108                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 109                /* Write Burst (WBS) */
 110                0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
 111                0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
 112                0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
 113                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 114                /* Refresh Timer (RTS) */
 115                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 116                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
 117                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 118                /* Exception Condition (EXS) */
 119                0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 120        };
 121
 122        upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
 123
 124        /* Set LUPWAIT to be active low and enabled */
 125        out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
 126
 127        return rc;
 128}
 129
 130#if defined(CONFIG_OF_BOARD_SETUP)
 131void ft_board_setup(void *blob, bd_t *bd)
 132{
 133        ft_cpu_setup(blob, bd);
 134#ifdef CONFIG_PCI
 135        ft_pci_setup(blob, bd);
 136#endif
 137}
 138#endif
 139#else /* CONFIG_NAND_SPL */
 140void board_init_f(ulong bootflag)
 141{
 142        NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
 143                                CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 144        puts("NAND boot... ");
 145        init_timebase();
 146        initdram(0);
 147        relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
 148                                  CONFIG_SYS_NAND_U_BOOT_RELOC);
 149}
 150
 151void board_init_r(gd_t *gd, ulong dest_addr)
 152{
 153        nand_boot();
 154}
 155
 156void putc(char c)
 157{
 158        if (gd->flags & GD_FLG_SILENT)
 159                return;
 160
 161        if (c == '\n')
 162                NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
 163
 164        NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
 165}
 166#endif
 167