LXR uboot/drivers/i2c/mxc

   1/*
   2 * i2c driver for Freescale i.MX series
   3 *
   4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
   6 *
   7 * Based on i2c-imx.c from linux kernel:
   8 *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
   9 *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  10 *  Copyright (C) 2007 RightHand Technologies, Inc.
  11 *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  12 *
  13 *
  14 * See file CREDITS for list of people who contributed to this
  15 * project.
  16 *
  17 * This program is free software; you can redistribute it and/or
  18 * modify it under the terms of the GNU General Public License as
  19 * published by the Free Software Foundation; either version 2 of
  20 * the License, or (at your option) any later version.
  21 *
  22 * This program is distributed in the hope that it will be useful,
  23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  25 * GNU General Public License for more details.
  26 *
  27 * You should have received a copy of the GNU General Public License
  28 * along with this program; if not, write to the Free Software
  29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30 * MA 02111-1307 USA
  31 */
  32
  33#include <common.h>
  34#include <asm/io.h>
  35
  36#if defined(CONFIG_HARD_I2C)
  37
  38#include <asm/arch/clock.h>
  39#include <asm/arch/imx-regs.h>
  40#include <i2c.h>
  41
  42struct mxc_i2c_regs {
  43        uint32_t        iadr;
  44        uint32_t        ifdr;
  45        uint32_t        i2cr;
  46        uint32_t        i2sr;
  47        uint32_t        i2dr;
  48};
  49
  50#define I2CR_IEN        (1 << 7)
  51#define I2CR_IIEN       (1 << 6)
  52#define I2CR_MSTA       (1 << 5)
  53#define I2CR_MTX        (1 << 4)
  54#define I2CR_TX_NO_AK   (1 << 3)
  55#define I2CR_RSTA       (1 << 2)
  56
  57#define I2SR_ICF        (1 << 7)
  58#define I2SR_IBB        (1 << 5)
  59#define I2SR_IIF        (1 << 1)
  60#define I2SR_RX_NO_AK   (1 << 0)
  61
  62#if defined(CONFIG_SYS_I2C_MX31_PORT1)
  63#define I2C_BASE        0x43f80000
  64#define I2C_CLK_OFFSET  26
  65#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
  66#define I2C_BASE        0x43f98000
  67#define I2C_CLK_OFFSET  28
  68#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
  69#define I2C_BASE        0x43f84000
  70#define I2C_CLK_OFFSET  30
  71#elif defined(CONFIG_SYS_I2C_MX53_PORT1)
  72#define I2C_BASE        I2C1_BASE_ADDR
  73#elif defined(CONFIG_SYS_I2C_MX53_PORT2)
  74#define I2C_BASE        I2C2_BASE_ADDR
  75#elif defined(CONFIG_SYS_I2C_MX35_PORT1)
  76#define I2C_BASE        I2C_BASE_ADDR
  77#elif defined(CONFIG_SYS_I2C_MX35_PORT2)
  78#define I2C_BASE        I2C2_BASE_ADDR
  79#elif defined(CONFIG_SYS_I2C_MX35_PORT3)
  80#define I2C_BASE        I2C3_BASE_ADDR
  81#else
  82#error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver"
  83#endif
  84
  85#define I2C_MAX_TIMEOUT         10000
  86
  87static u16 i2c_clk_div[50][2] = {
  88        { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
  89        { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
  90        { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
  91        { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
  92        { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
  93        { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
  94        { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
  95        { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
  96        { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
  97        { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
  98        { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  99        { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 100        { 3072, 0x1E }, { 3840, 0x1F }
 101};
 102
 103/*
 104 * Calculate and set proper clock divider
 105 */
 106static uint8_t i2c_imx_get_clk(unsigned int rate)
 107{
 108        unsigned int i2c_clk_rate;
 109        unsigned int div;
 110        u8 clk_div;
 111
 112#if defined(CONFIG_MX31)
 113        struct clock_control_regs *sc_regs =
 114                (struct clock_control_regs *)CCM_BASE;
 115
 116        /* start the required I2C clock */
 117        writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET),
 118                &sc_regs->cgr0);
 119#endif
 120
 121        /* Divider value calculation */
 122        i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
 123        div = (i2c_clk_rate + rate - 1) / rate;
 124        if (div < i2c_clk_div[0][0])
 125                clk_div = 0;
 126        else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 127                clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 128        else
 129                for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 130                        ;
 131
 132        /* Store divider value */
 133        return clk_div;
 134}
 135
 136/*
 137 * Reset I2C Controller
 138 */
 139void i2c_reset(void)
 140{
 141        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 142
 143        writeb(0, &i2c_regs->i2cr);     /* Reset module */
 144        writeb(0, &i2c_regs->i2sr);
 145}
 146
 147/*
 148 * Init I2C Bus
 149 */
 150void i2c_init(int speed, int unused)
 151{
 152        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 153        u8 clk_idx = i2c_imx_get_clk(speed);
 154        u8 idx = i2c_clk_div[clk_idx][1];
 155
 156        /* Store divider value */
 157        writeb(idx, &i2c_regs->ifdr);
 158
 159        i2c_reset();
 160}
 161
 162/*
 163 * Set I2C Speed
 164 */
 165int i2c_set_bus_speed(unsigned int speed)
 166{
 167        i2c_init(speed, 0);
 168        return 0;
 169}
 170
 171/*
 172 * Get I2C Speed
 173 */
 174unsigned int i2c_get_bus_speed(void)
 175{
 176        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 177        u8 clk_idx = readb(&i2c_regs->ifdr);
 178        u8 clk_div;
 179
 180        for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
 181                ;
 182
 183        return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
 184}
 185
 186/*
 187 * Wait for bus to be busy (or free if for_busy = 0)
 188 *
 189 * for_busy = 1: Wait for IBB to be asserted
 190 * for_busy = 0: Wait for IBB to be de-asserted
 191 */
 192int i2c_imx_bus_busy(int for_busy)
 193{
 194        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 195        unsigned int temp;
 196
 197        int timeout = I2C_MAX_TIMEOUT;
 198
 199        while (timeout--) {
 200                temp = readb(&i2c_regs->i2sr);
 201
 202                if (for_busy && (temp & I2SR_IBB))
 203                        return 0;
 204                if (!for_busy && !(temp & I2SR_IBB))
 205                        return 0;
 206
 207                udelay(1);
 208        }
 209
 210        return 1;
 211}
 212
 213/*
 214 * Wait for transaction to complete
 215 */
 216int i2c_imx_trx_complete(void)
 217{
 218        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 219        int timeout = I2C_MAX_TIMEOUT;
 220
 221        while (timeout--) {
 222                if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
 223                        writeb(0, &i2c_regs->i2sr);
 224                        return 0;
 225                }
 226
 227                udelay(1);
 228        }
 229
 230        return 1;
 231}
 232
 233/*
 234 * Check if the transaction was ACKed
 235 */
 236int i2c_imx_acked(void)
 237{
 238        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 239
 240        return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
 241}
 242
 243/*
 244 * Start the controller
 245 */
 246int i2c_imx_start(void)
 247{
 248        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 249        unsigned int temp = 0;
 250        int result;
 251        int speed = i2c_get_bus_speed();
 252        u8 clk_idx = i2c_imx_get_clk(speed);
 253        u8 idx = i2c_clk_div[clk_idx][1];
 254
 255        /* Store divider value */
 256        writeb(idx, &i2c_regs->ifdr);
 257
 258        /* Enable I2C controller */
 259        writeb(0, &i2c_regs->i2sr);
 260        writeb(I2CR_IEN, &i2c_regs->i2cr);
 261
 262        /* Wait controller to be stable */
 263        udelay(50);
 264
 265        /* Start I2C transaction */
 266        temp = readb(&i2c_regs->i2cr);
 267        temp |= I2CR_MSTA;
 268        writeb(temp, &i2c_regs->i2cr);
 269
 270        result = i2c_imx_bus_busy(1);
 271        if (result)
 272                return result;
 273
 274        temp |= I2CR_MTX | I2CR_TX_NO_AK;
 275        writeb(temp, &i2c_regs->i2cr);
 276
 277        return 0;
 278}
 279
 280/*
 281 * Stop the controller
 282 */
 283void i2c_imx_stop(void)
 284{
 285        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 286        unsigned int temp = 0;
 287
 288        /* Stop I2C transaction */
 289        temp = readb(&i2c_regs->i2cr);
 290        temp |= ~(I2CR_MSTA | I2CR_MTX);
 291        writeb(temp, &i2c_regs->i2cr);
 292
 293        i2c_imx_bus_busy(0);
 294
 295        /* Disable I2C controller */
 296        writeb(0, &i2c_regs->i2cr);
 297}
 298
 299/*
 300 * Set chip address and access mode
 301 *
 302 * read = 1: READ access
 303 * read = 0: WRITE access
 304 */
 305int i2c_imx_set_chip_addr(uchar chip, int read)
 306{
 307        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 308        int ret;
 309
 310        writeb((chip << 1) | read, &i2c_regs->i2dr);
 311
 312        ret = i2c_imx_trx_complete();
 313        if (ret)
 314                return ret;
 315
 316        ret = i2c_imx_acked();
 317        if (ret)
 318                return ret;
 319
 320        return ret;
 321}
 322
 323/*
 324 * Write register address
 325 */
 326int i2c_imx_set_reg_addr(uint addr, int alen)
 327{
 328        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 329        int ret = 0;
 330
 331        while (alen--) {
 332                writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
 333
 334                ret = i2c_imx_trx_complete();
 335                if (ret)
 336                        break;
 337
 338                ret = i2c_imx_acked();
 339                if (ret)
 340                        break;
 341        }
 342
 343        return ret;
 344}
 345
 346/*
 347 * Try if a chip add given address responds (probe the chip)
 348 */
 349int i2c_probe(uchar chip)
 350{
 351        int ret;
 352
 353        ret = i2c_imx_start();
 354        if (ret)
 355                return ret;
 356
 357        ret = i2c_imx_set_chip_addr(chip, 0);
 358        if (ret)
 359                return ret;
 360
 361        i2c_imx_stop();
 362
 363        return ret;
 364}
 365
 366/*
 367 * Read data from I2C device
 368 */
 369int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
 370{
 371        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 372        int ret;
 373        unsigned int temp;
 374        int i;
 375
 376        ret = i2c_imx_start();
 377        if (ret)
 378                return ret;
 379
 380        /* write slave address */
 381        ret = i2c_imx_set_chip_addr(chip, 0);
 382        if (ret)
 383                return ret;
 384
 385        ret = i2c_imx_set_reg_addr(addr, alen);
 386        if (ret)
 387                return ret;
 388
 389        temp = readb(&i2c_regs->i2cr);
 390        temp |= I2CR_RSTA;
 391        writeb(temp, &i2c_regs->i2cr);
 392
 393        ret = i2c_imx_set_chip_addr(chip, 1);
 394        if (ret)
 395                return ret;
 396
 397        /* setup bus to read data */
 398        temp = readb(&i2c_regs->i2cr);
 399        temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 400        if (len == 1)
 401                temp |= I2CR_TX_NO_AK;
 402        writeb(temp, &i2c_regs->i2cr);
 403        readb(&i2c_regs->i2dr);
 404
 405        /* read data */
 406        for (i = 0; i < len; i++) {
 407                ret = i2c_imx_trx_complete();
 408                if (ret)
 409                        return ret;
 410
 411                /*
 412                 * It must generate STOP before read I2DR to prevent
 413                 * controller from generating another clock cycle
 414                 */
 415                if (i == (len - 1)) {
 416                        temp = readb(&i2c_regs->i2cr);
 417                        temp &= ~(I2CR_MSTA | I2CR_MTX);
 418                        writeb(temp, &i2c_regs->i2cr);
 419                        i2c_imx_bus_busy(0);
 420                } else if (i == (len - 2)) {
 421                        temp = readb(&i2c_regs->i2cr);
 422                        temp |= I2CR_TX_NO_AK;
 423                        writeb(temp, &i2c_regs->i2cr);
 424                }
 425
 426                buf[i] = readb(&i2c_regs->i2dr);
 427        }
 428
 429        i2c_imx_stop();
 430
 431        return ret;
 432}
 433
 434/*
 435 * Write data to I2C device
 436 */
 437int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 438{
 439        struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
 440        int ret;
 441        int i;
 442
 443        ret = i2c_imx_start();
 444        if (ret)
 445                return ret;
 446
 447        /* write slave address */
 448        ret = i2c_imx_set_chip_addr(chip, 0);
 449        if (ret)
 450                return ret;
 451
 452        ret = i2c_imx_set_reg_addr(addr, alen);
 453        if (ret)
 454                return ret;
 455
 456        for (i = 0; i < len; i++) {
 457                writeb(buf[i], &i2c_regs->i2dr);
 458
 459                ret = i2c_imx_trx_complete();
 460                if (ret)
 461                        return ret;
 462
 463                ret = i2c_imx_acked();
 464                if (ret)
 465                        return ret;
 466        }
 467
 468        i2c_imx_stop();
 469
 470        return ret;
 471}
 472#endif /* CONFIG_HARD_I2C */
 473