uboot/drivers/pci/pci.c
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   1/*
   2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3 * Andreas Heppel <aheppel@sysgo.de>
   4 *
   5 * (C) Copyright 2002, 2003
   6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/*
  28 * PCI routines
  29 */
  30
  31#include <common.h>
  32
  33#include <command.h>
  34#include <asm/processor.h>
  35#include <asm/io.h>
  36#include <pci.h>
  37
  38#define PCI_HOSE_OP(rw, size, type)                                     \
  39int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  40                                  pci_dev_t dev,                        \
  41                                  int offset, type value)               \
  42{                                                                       \
  43        return hose->rw##_##size(hose, dev, offset, value);             \
  44}
  45
  46PCI_HOSE_OP(read, byte, u8 *)
  47PCI_HOSE_OP(read, word, u16 *)
  48PCI_HOSE_OP(read, dword, u32 *)
  49PCI_HOSE_OP(write, byte, u8)
  50PCI_HOSE_OP(write, word, u16)
  51PCI_HOSE_OP(write, dword, u32)
  52
  53#define PCI_OP(rw, size, type, error_code)                              \
  54int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  55{                                                                       \
  56        struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  57                                                                        \
  58        if (!hose)                                                      \
  59        {                                                               \
  60                error_code;                                             \
  61                return -1;                                              \
  62        }                                                               \
  63                                                                        \
  64        return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  65}
  66
  67PCI_OP(read, byte, u8 *, *value = 0xff)
  68PCI_OP(read, word, u16 *, *value = 0xffff)
  69PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  70PCI_OP(write, byte, u8, )
  71PCI_OP(write, word, u16, )
  72PCI_OP(write, dword, u32, )
  73
  74#define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  75int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  76                                        pci_dev_t dev,                  \
  77                                        int offset, type val)           \
  78{                                                                       \
  79        u32 val32;                                                      \
  80                                                                        \
  81        if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  82                *val = -1;                                              \
  83                return -1;                                              \
  84        }                                                               \
  85                                                                        \
  86        *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  87                                                                        \
  88        return 0;                                                       \
  89}
  90
  91#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  92int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  93                                             pci_dev_t dev,             \
  94                                             int offset, type val)      \
  95{                                                                       \
  96        u32 val32, mask, ldata, shift;                                  \
  97                                                                        \
  98        if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  99                return -1;                                              \
 100                                                                        \
 101        shift = ((offset & (int)off_mask) * 8);                         \
 102        ldata = (((unsigned long)val) & val_mask) << shift;             \
 103        mask = val_mask << shift;                                       \
 104        val32 = (val32 & ~mask) | ldata;                                \
 105                                                                        \
 106        if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
 107                return -1;                                              \
 108                                                                        \
 109        return 0;                                                       \
 110}
 111
 112PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 113PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 114PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 115PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 116
 117/* Get a virtual address associated with a BAR region */
 118void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 119{
 120        pci_addr_t pci_bus_addr;
 121        u32 bar_response;
 122
 123        /* read BAR address */
 124        pci_read_config_dword(pdev, bar, &bar_response);
 125        pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 126
 127        /*
 128         * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 129         * isn't actualy used on any platform because u-boot assumes a static
 130         * linear mapping.  In the future, this could read the BAR size
 131         * and pass that as the size if needed.
 132         */
 133        return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 134}
 135
 136/*
 137 *
 138 */
 139
 140static struct pci_controller* hose_head;
 141
 142void pci_register_hose(struct pci_controller* hose)
 143{
 144        struct pci_controller **phose = &hose_head;
 145
 146        while(*phose)
 147                phose = &(*phose)->next;
 148
 149        hose->next = NULL;
 150
 151        *phose = hose;
 152}
 153
 154struct pci_controller *pci_bus_to_hose (int bus)
 155{
 156        struct pci_controller *hose;
 157
 158        for (hose = hose_head; hose; hose = hose->next)
 159                if (bus >= hose->first_busno && bus <= hose->last_busno)
 160                        return hose;
 161
 162        printf("pci_bus_to_hose() failed\n");
 163        return NULL;
 164}
 165
 166struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 167{
 168        struct pci_controller *hose;
 169
 170        for (hose = hose_head; hose; hose = hose->next) {
 171                if (hose->cfg_addr == cfg_addr)
 172                        return hose;
 173        }
 174
 175        return NULL;
 176}
 177
 178int pci_last_busno(void)
 179{
 180        struct pci_controller *hose = hose_head;
 181
 182        if (!hose)
 183                return -1;
 184
 185        while (hose->next)
 186                hose = hose->next;
 187
 188        return hose->last_busno;
 189}
 190
 191pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 192{
 193        struct pci_controller * hose;
 194        u16 vendor, device;
 195        u8 header_type;
 196        pci_dev_t bdf;
 197        int i, bus, found_multi = 0;
 198
 199        for (hose = hose_head; hose; hose = hose->next)
 200        {
 201#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 202                for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 203#else
 204                for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 205#endif
 206                        for (bdf = PCI_BDF(bus,0,0);
 207#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
 208                             bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 209#else
 210                             bdf < PCI_BDF(bus+1,0,0);
 211#endif
 212                             bdf += PCI_BDF(0,0,1))
 213                        {
 214                                if (!PCI_FUNC(bdf)) {
 215                                        pci_read_config_byte(bdf,
 216                                                             PCI_HEADER_TYPE,
 217                                                             &header_type);
 218
 219                                        found_multi = header_type & 0x80;
 220                                } else {
 221                                        if (!found_multi)
 222                                                continue;
 223                                }
 224
 225                                pci_read_config_word(bdf,
 226                                                     PCI_VENDOR_ID,
 227                                                     &vendor);
 228                                pci_read_config_word(bdf,
 229                                                     PCI_DEVICE_ID,
 230                                                     &device);
 231
 232                                for (i=0; ids[i].vendor != 0; i++)
 233                                        if (vendor == ids[i].vendor &&
 234                                            device == ids[i].device)
 235                                        {
 236                                                if (index <= 0)
 237                                                        return bdf;
 238
 239                                                index--;
 240                                        }
 241                        }
 242        }
 243
 244        return (-1);
 245}
 246
 247pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 248{
 249        static struct pci_device_id ids[2] = {{}, {0, 0}};
 250
 251        ids[0].vendor = vendor;
 252        ids[0].device = device;
 253
 254        return pci_find_devices(ids, index);
 255}
 256
 257/*
 258 *
 259 */
 260
 261int __pci_hose_phys_to_bus (struct pci_controller *hose,
 262                                phys_addr_t phys_addr,
 263                                unsigned long flags,
 264                                unsigned long skip_mask,
 265                                pci_addr_t *ba)
 266{
 267        struct pci_region *res;
 268        pci_addr_t bus_addr;
 269        int i;
 270
 271        for (i = 0; i < hose->region_count; i++) {
 272                res = &hose->regions[i];
 273
 274                if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 275                        continue;
 276
 277                if (res->flags & skip_mask)
 278                        continue;
 279
 280                bus_addr = phys_addr - res->phys_start + res->bus_start;
 281
 282                if (bus_addr >= res->bus_start &&
 283                        bus_addr < res->bus_start + res->size) {
 284                        *ba = bus_addr;
 285                        return 0;
 286                }
 287        }
 288
 289        return 1;
 290}
 291
 292pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 293                                    phys_addr_t phys_addr,
 294                                    unsigned long flags)
 295{
 296        pci_addr_t bus_addr = 0;
 297        int ret;
 298
 299        if (!hose) {
 300                puts ("pci_hose_phys_to_bus: invalid hose\n");
 301                return bus_addr;
 302        }
 303
 304        /* if PCI_REGION_MEM is set we do a two pass search with preference
 305         * on matches that don't have PCI_REGION_SYS_MEMORY set */
 306        if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 307                ret = __pci_hose_phys_to_bus(hose, phys_addr,
 308                                flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 309                if (!ret)
 310                        return bus_addr;
 311        }
 312
 313        ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 314
 315        if (ret)
 316                puts ("pci_hose_phys_to_bus: invalid physical address\n");
 317
 318        return bus_addr;
 319}
 320
 321int __pci_hose_bus_to_phys (struct pci_controller *hose,
 322                                pci_addr_t bus_addr,
 323                                unsigned long flags,
 324                                unsigned long skip_mask,
 325                                phys_addr_t *pa)
 326{
 327        struct pci_region *res;
 328        int i;
 329
 330        for (i = 0; i < hose->region_count; i++) {
 331                res = &hose->regions[i];
 332
 333                if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 334                        continue;
 335
 336                if (res->flags & skip_mask)
 337                        continue;
 338
 339                if (bus_addr >= res->bus_start &&
 340                        bus_addr < res->bus_start + res->size) {
 341                        *pa = (bus_addr - res->bus_start + res->phys_start);
 342                        return 0;
 343                }
 344        }
 345
 346        return 1;
 347}
 348
 349phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 350                                 pci_addr_t bus_addr,
 351                                 unsigned long flags)
 352{
 353        phys_addr_t phys_addr = 0;
 354        int ret;
 355
 356        if (!hose) {
 357                puts ("pci_hose_bus_to_phys: invalid hose\n");
 358                return phys_addr;
 359        }
 360
 361        /* if PCI_REGION_MEM is set we do a two pass search with preference
 362         * on matches that don't have PCI_REGION_SYS_MEMORY set */
 363        if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 364                ret = __pci_hose_bus_to_phys(hose, bus_addr,
 365                                flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 366                if (!ret)
 367                        return phys_addr;
 368        }
 369
 370        ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 371
 372        if (ret)
 373                puts ("pci_hose_bus_to_phys: invalid physical address\n");
 374
 375        return phys_addr;
 376}
 377
 378/*
 379 *
 380 */
 381
 382int pci_hose_config_device(struct pci_controller *hose,
 383                           pci_dev_t dev,
 384                           unsigned long io,
 385                           pci_addr_t mem,
 386                           unsigned long command)
 387{
 388        unsigned int bar_response, old_command;
 389        pci_addr_t bar_value;
 390        pci_size_t bar_size;
 391        unsigned char pin;
 392        int bar, found_mem64;
 393
 394        debug ("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n",
 395                io, (u64)mem, command);
 396
 397        pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
 398
 399        for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 400                pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
 401                pci_hose_read_config_dword (hose, dev, bar, &bar_response);
 402
 403                if (!bar_response)
 404                        continue;
 405
 406                found_mem64 = 0;
 407
 408                /* Check the BAR type and set our address mask */
 409                if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 410                        bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 411                        /* round up region base address to a multiple of size */
 412                        io = ((io - 1) | (bar_size - 1)) + 1;
 413                        bar_value = io;
 414                        /* compute new region base address */
 415                        io = io + bar_size;
 416                } else {
 417                        if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 418                                PCI_BASE_ADDRESS_MEM_TYPE_64) {
 419                                u32 bar_response_upper;
 420                                u64 bar64;
 421                                pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
 422                                pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
 423
 424                                bar64 = ((u64)bar_response_upper << 32) | bar_response;
 425
 426                                bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 427                                found_mem64 = 1;
 428                        } else {
 429                                bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 430                        }
 431
 432                        /* round up region base address to multiple of size */
 433                        mem = ((mem - 1) | (bar_size - 1)) + 1;
 434                        bar_value = mem;
 435                        /* compute new region base address */
 436                        mem = mem + bar_size;
 437                }
 438
 439                /* Write it out and update our limit */
 440                pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 441
 442                if (found_mem64) {
 443                        bar += 4;
 444#ifdef CONFIG_SYS_PCI_64BIT
 445                        pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 446#else
 447                        pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
 448#endif
 449                }
 450        }
 451
 452        /* Configure Cache Line Size Register */
 453        pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 454
 455        /* Configure Latency Timer */
 456        pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
 457
 458        /* Disable interrupt line, if device says it wants to use interrupts */
 459        pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
 460        if (pin != 0) {
 461                pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
 462        }
 463
 464        pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
 465        pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
 466                                     (old_command & 0xffff0000) | command);
 467
 468        return 0;
 469}
 470
 471/*
 472 *
 473 */
 474
 475struct pci_config_table *pci_find_config(struct pci_controller *hose,
 476                                         unsigned short class,
 477                                         unsigned int vendor,
 478                                         unsigned int device,
 479                                         unsigned int bus,
 480                                         unsigned int dev,
 481                                         unsigned int func)
 482{
 483        struct pci_config_table *table;
 484
 485        for (table = hose->config_table; table && table->vendor; table++) {
 486                if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 487                    (table->device == PCI_ANY_ID || table->device == device) &&
 488                    (table->class  == PCI_ANY_ID || table->class  == class)  &&
 489                    (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 490                    (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 491                    (table->func   == PCI_ANY_ID || table->func   == func)) {
 492                        return table;
 493                }
 494        }
 495
 496        return NULL;
 497}
 498
 499void pci_cfgfunc_config_device(struct pci_controller *hose,
 500                               pci_dev_t dev,
 501                               struct pci_config_table *entry)
 502{
 503        pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
 504}
 505
 506void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 507                            pci_dev_t dev, struct pci_config_table *entry)
 508{
 509}
 510
 511/*
 512 *
 513 */
 514
 515/* HJF: Changed this to return int. I think this is required
 516 * to get the correct result when scanning bridges
 517 */
 518extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 519
 520#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 521const char * pci_class_str(u8 class)
 522{
 523        switch (class) {
 524        case PCI_CLASS_NOT_DEFINED:
 525                return "Build before PCI Rev2.0";
 526                break;
 527        case PCI_BASE_CLASS_STORAGE:
 528                return "Mass storage controller";
 529                break;
 530        case PCI_BASE_CLASS_NETWORK:
 531                return "Network controller";
 532                break;
 533        case PCI_BASE_CLASS_DISPLAY:
 534                return "Display controller";
 535                break;
 536        case PCI_BASE_CLASS_MULTIMEDIA:
 537                return "Multimedia device";
 538                break;
 539        case PCI_BASE_CLASS_MEMORY:
 540                return "Memory controller";
 541                break;
 542        case PCI_BASE_CLASS_BRIDGE:
 543                return "Bridge device";
 544                break;
 545        case PCI_BASE_CLASS_COMMUNICATION:
 546                return "Simple comm. controller";
 547                break;
 548        case PCI_BASE_CLASS_SYSTEM:
 549                return "Base system peripheral";
 550                break;
 551        case PCI_BASE_CLASS_INPUT:
 552                return "Input device";
 553                break;
 554        case PCI_BASE_CLASS_DOCKING:
 555                return "Docking station";
 556                break;
 557        case PCI_BASE_CLASS_PROCESSOR:
 558                return "Processor";
 559                break;
 560        case PCI_BASE_CLASS_SERIAL:
 561                return "Serial bus controller";
 562                break;
 563        case PCI_BASE_CLASS_INTELLIGENT:
 564                return "Intelligent controller";
 565                break;
 566        case PCI_BASE_CLASS_SATELLITE:
 567                return "Satellite controller";
 568                break;
 569        case PCI_BASE_CLASS_CRYPT:
 570                return "Cryptographic device";
 571                break;
 572        case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 573                return "DSP";
 574                break;
 575        case PCI_CLASS_OTHERS:
 576                return "Does not fit any class";
 577                break;
 578        default:
 579        return  "???";
 580                break;
 581        };
 582}
 583#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 584
 585int __pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 586{
 587        /*
 588         * Check if pci device should be skipped in configuration
 589         */
 590        if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 591#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 592                /*
 593                 * Only skip configuration if "pciconfighost" is not set
 594                 */
 595                if (getenv("pciconfighost") == NULL)
 596                        return 1;
 597#else
 598                return 1;
 599#endif
 600        }
 601
 602        return 0;
 603}
 604int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 605        __attribute__((weak, alias("__pci_skip_dev")));
 606
 607#ifdef CONFIG_PCI_SCAN_SHOW
 608int __pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 609{
 610        if (dev == PCI_BDF(hose->first_busno, 0, 0))
 611                return 0;
 612
 613        return 1;
 614}
 615int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 616        __attribute__((weak, alias("__pci_print_dev")));
 617#endif /* CONFIG_PCI_SCAN_SHOW */
 618
 619int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 620{
 621        unsigned int sub_bus, found_multi=0;
 622        unsigned short vendor, device, class;
 623        unsigned char header_type;
 624        struct pci_config_table *cfg;
 625        pci_dev_t dev;
 626#ifdef CONFIG_PCI_SCAN_SHOW
 627        static int indent = 0;
 628#endif
 629
 630        sub_bus = bus;
 631
 632        for (dev =  PCI_BDF(bus,0,0);
 633             dev <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
 634             dev += PCI_BDF(0,0,1)) {
 635
 636                if (pci_skip_dev(hose, dev))
 637                        continue;
 638
 639                if (PCI_FUNC(dev) && !found_multi)
 640                        continue;
 641
 642                pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 643
 644                pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 645
 646                if (vendor == 0xffff || vendor == 0x0000)
 647                        continue;
 648
 649                if (!PCI_FUNC(dev))
 650                        found_multi = header_type & 0x80;
 651
 652                debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 653                        PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
 654
 655                pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 656                pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 657
 658#ifdef CONFIG_PCI_SCAN_SHOW
 659                indent++;
 660
 661                /* Print leading space, including bus indentation */
 662                printf("%*c", indent + 1, ' ');
 663
 664                if (pci_print_dev(hose, dev)) {
 665                        printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 666                               PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 667                               vendor, device, pci_class_str(class >> 8));
 668                }
 669#endif
 670
 671                cfg = pci_find_config(hose, class, vendor, device,
 672                                      PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 673                if (cfg) {
 674                        cfg->config_device(hose, dev, cfg);
 675                        sub_bus = max(sub_bus, hose->current_busno);
 676#ifdef CONFIG_PCI_PNP
 677                } else {
 678                        int n = pciauto_config_device(hose, dev);
 679
 680                        sub_bus = max(sub_bus, n);
 681#endif
 682                }
 683
 684#ifdef CONFIG_PCI_SCAN_SHOW
 685                indent--;
 686#endif
 687
 688                if (hose->fixup_irq)
 689                        hose->fixup_irq(hose, dev);
 690        }
 691
 692        return sub_bus;
 693}
 694
 695int pci_hose_scan(struct pci_controller *hose)
 696{
 697#if defined(CONFIG_PCI_BOOTDELAY)
 698        static int pcidelay_done;
 699        char *s;
 700        int i;
 701
 702        if (!pcidelay_done) {
 703                /* wait "pcidelay" ms (if defined)... */
 704                s = getenv("pcidelay");
 705                if (s) {
 706                        int val = simple_strtoul(s, NULL, 10);
 707                        for (i = 0; i < val; i++)
 708                                udelay(1000);
 709                }
 710                pcidelay_done = 1;
 711        }
 712#endif /* CONFIG_PCI_BOOTDELAY */
 713
 714        /* Start scan at current_busno.
 715         * PCIe will start scan at first_busno+1.
 716         */
 717        /* For legacy support, ensure current>=first */
 718        if (hose->first_busno > hose->current_busno)
 719                hose->current_busno = hose->first_busno;
 720#ifdef CONFIG_PCI_PNP
 721        pciauto_config_init(hose);
 722#endif
 723        return pci_hose_scan_bus(hose, hose->current_busno);
 724}
 725
 726void pci_init(void)
 727{
 728        hose_head = NULL;
 729
 730        /* now call board specific pci_init()... */
 731        pci_init_board();
 732}
 733