LXR uboot/drivers/spi/omap3

   1/*
   2 * Register definitions for the OMAP3 McSPI Controller
   3 *
   4 * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
   5 *
   6 * Parts taken from linux/drivers/spi/omap2_mcspi.c
   7 * Copyright (C) 2005, 2006 Nokia Corporation
   8 *
   9 * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
  10 *
  11 * See file CREDITS for list of people who contributed to this
  12 * project.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, write to the Free Software
  26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 * MA 02111-1307 USA
  28 */
  29
  30#ifndef _OMAP3_SPI_H_
  31#define _OMAP3_SPI_H_
  32
  33#define OMAP3_MCSPI1_BASE       0x48098000
  34#define OMAP3_MCSPI2_BASE       0x4809A000
  35#define OMAP3_MCSPI3_BASE       0x480B8000
  36#define OMAP3_MCSPI4_BASE       0x480BA000
  37
  38#define OMAP3_MCSPI_MAX_FREQ    48000000
  39
  40/* OMAP3 McSPI registers */
  41struct mcspi_channel {
  42        unsigned int chconf;            /* 0x2C, 0x40, 0x54, 0x68 */
  43        unsigned int chstat;            /* 0x30, 0x44, 0x58, 0x6C */
  44        unsigned int chctrl;            /* 0x34, 0x48, 0x5C, 0x70 */
  45        unsigned int tx;                /* 0x38, 0x4C, 0x60, 0x74 */
  46        unsigned int rx;                /* 0x3C, 0x50, 0x64, 0x78 */
  47};
  48
  49struct mcspi {
  50        unsigned char res1[0x10];
  51        unsigned int sysconfig;         /* 0x10 */
  52        unsigned int sysstatus;         /* 0x14 */
  53        unsigned int irqstatus;         /* 0x18 */
  54        unsigned int irqenable;         /* 0x1C */
  55        unsigned int wakeupenable;      /* 0x20 */
  56        unsigned int syst;              /* 0x24 */
  57        unsigned int modulctrl;         /* 0x28 */
  58        struct mcspi_channel channel[4]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */
  59                                        /* channel1: 0x40 - 0x50, bus 0 & 1 */
  60                                        /* channel2: 0x54 - 0x64, bus 0 & 1 */
  61                                        /* channel3: 0x68 - 0x78, bus 0 */
  62};
  63
  64/* per-register bitmasks */
  65#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3)
  66#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP (1 << 2)
  67#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE  (1 << 0)
  68#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
  69
  70#define OMAP3_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
  71
  72#define OMAP3_MCSPI_MODULCTRL_SINGLE    (1 << 0)
  73#define OMAP3_MCSPI_MODULCTRL_MS        (1 << 2)
  74#define OMAP3_MCSPI_MODULCTRL_STEST     (1 << 3)
  75
  76#define OMAP3_MCSPI_CHCONF_PHA          (1 << 0)
  77#define OMAP3_MCSPI_CHCONF_POL          (1 << 1)
  78#define OMAP3_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  79#define OMAP3_MCSPI_CHCONF_EPOL         (1 << 6)
  80#define OMAP3_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  81#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY  (0x01 << 12)
  82#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY  (0x02 << 12)
  83#define OMAP3_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  84#define OMAP3_MCSPI_CHCONF_DMAW         (1 << 14)
  85#define OMAP3_MCSPI_CHCONF_DMAR         (1 << 15)
  86#define OMAP3_MCSPI_CHCONF_DPE0         (1 << 16)
  87#define OMAP3_MCSPI_CHCONF_DPE1         (1 << 17)
  88#define OMAP3_MCSPI_CHCONF_IS           (1 << 18)
  89#define OMAP3_MCSPI_CHCONF_TURBO        (1 << 19)
  90#define OMAP3_MCSPI_CHCONF_FORCE        (1 << 20)
  91
  92#define OMAP3_MCSPI_CHSTAT_RXS          (1 << 0)
  93#define OMAP3_MCSPI_CHSTAT_TXS          (1 << 1)
  94#define OMAP3_MCSPI_CHSTAT_EOT          (1 << 2)
  95
  96#define OMAP3_MCSPI_CHCTRL_EN           (1 << 0)
  97
  98#define OMAP3_MCSPI_WAKEUPENABLE_WKEN   (1 << 0)
  99
 100struct omap3_spi_slave {
 101        struct spi_slave slave;
 102        struct mcspi *regs;
 103        unsigned int freq;
 104        unsigned int mode;
 105};
 106
 107static inline struct omap3_spi_slave *to_omap3_spi(struct spi_slave *slave)
 108{
 109        return container_of(slave, struct omap3_spi_slave, slave);
 110}
 111
 112int omap3_spi_txrx(struct spi_slave *slave, unsigned int len, const u8 *txp,
 113                        u8 *rxp, unsigned long flags);
 114int omap3_spi_write(struct spi_slave *slave, unsigned int len, const u8 *txp,
 115                    unsigned long flags);
 116int omap3_spi_read(struct spi_slave *slave, unsigned int len, u8 *rxp,
 117                   unsigned long flags);
 118
 119#endif /* _OMAP3_SPI_H_ */
 120