1/* 2 * Copyright (C) 2004-2005 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Analogue&Micro Adder boards family. 6 * Tested on AdderII and Adder87x. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26#ifndef __CONFIG_H 27#define __CONFIG_H 28 29#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) 30#define CONFIG_MPC875 31#endif 32 33#define CONFIG_ADDER /* Analogue&Micro Adder board */ 34 35#define CONFIG_SYS_TEXT_BASE 0xFE000000 36 37#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 38#define CONFIG_BAUDRATE 38400 39 40#define CONFIG_ETHER_ON_FEC1 41#define CONFIG_ETHER_ON_FEC2 42#define CONFIG_HAS_ETH0 43#define CONFIG_HAS_ETH1 44 45#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) 46#define CONFIG_SYS_DISCOVER_PHY 47#define CONFIG_MII_INIT 1 48#define FEC_ENET 49#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ 50 51#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ 52#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 53#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 54#ifdef CONFIG_MPC852T 55#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000 56#else 57#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 58#endif /* CONFIG_MPC852T */ 59 60 61/* 62 * BOOTP options 63 */ 64#define CONFIG_BOOTP_BOOTFILESIZE 65#define CONFIG_BOOTP_BOOTPATH 66#define CONFIG_BOOTP_GATEWAY 67#define CONFIG_BOOTP_HOSTNAME 68 69 70/* 71 * Command line configuration. 72 */ 73#include <config_cmd_default.h> 74 75#define CONFIG_CMD_DHCP 76#define CONFIG_CMD_IMMAP 77#define CONFIG_CMD_MII 78#define CONFIG_CMD_PING 79 80 81#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ 82#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ 83#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" 84 85#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 86#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 87 88/*----------------------------------------------------------------------- 89 * Miscellaneous configurable options 90 */ 91#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 92#define CONFIG_SYS_HUSH_PARSER 93#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 94#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 95#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 96#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 97#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 98#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 99 100#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ 101 102#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 103 104#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 105 106/*----------------------------------------------------------------------- 107 * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) 108 */ 109#define CONFIG_SYS_SDRAM_BASE 0x00000000 110#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ 111 112#define CONFIG_SYS_MAMR 0x00002114 113 114/* 115 * 4096 Up to 4096 SDRAM rows 116 * 1000 factor s -> ms 117 * 32 PTP (pre-divider from MPTPR) 118 * 4 Number of refresh cycles per period 119 * 64 Refresh cycle in ms per number of rows 120 */ 121#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 122 123#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 124#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ 125 126#define CONFIG_SYS_RESET_ADDRESS 0x09900000 127 128/*----------------------------------------------------------------------- 129 * For booting Linux, the board info and command line data 130 * have to be in the first 8 MB of memory, since this is 131 * the maximum mapped by the Linux kernel during initialization. 132 */ 133#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 134 135#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 136#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ 137#ifdef CONFIG_BZIP2 138#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ 139#else 140#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 141#endif /* CONFIG_BZIP2 */ 142 143/*----------------------------------------------------------------------- 144 * Flash organisation 145 */ 146#define CONFIG_SYS_FLASH_BASE 0xFE000000 147#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 148#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 149#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 150#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ 151 152/* Environment is in flash */ 153#define CONFIG_ENV_IS_IN_FLASH 154#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ 155#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 156 157#define CONFIG_ENV_OVERWRITE 158 159#define CONFIG_SYS_OR0_PRELIM 0xFF000774 160#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) 161 162#define CONFIG_SYS_DIRECT_FLASH_TFTP 163 164/*----------------------------------------------------------------------- 165 * Internal Memory Map Register 166 */ 167#define CONFIG_SYS_IMMR 0xFF000000 168 169/*----------------------------------------------------------------------- 170 * Definitions for initial stack pointer and data area (in DPRAM) 171 */ 172#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 173#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 174#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 176 177/*----------------------------------------------------------------------- 178 * Configuration registers 179 */ 180#ifdef CONFIG_WATCHDOG 181#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 182 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ 183 SYPCR_SWP) 184#else 185#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 186 SYPCR_SWF | SYPCR_SWP) 187#endif /* CONFIG_WATCHDOG */ 188 189#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) 190 191/* TBSCR - Time Base Status and Control Register */ 192#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) 193 194/* PISCR - Periodic Interrupt Status and Control */ 195#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 196 197/* PLPRCR - PLL, Low-Power, and Reset Control Register */ 198/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */ 199 200/* SCCR - System Clock and reset Control Register */ 201#define SCCR_MASK SCCR_EBDF11 202#define CONFIG_SYS_SCCR SCCR_RTSEL 203 204#define CONFIG_SYS_DER 0 205 206/*----------------------------------------------------------------------- 207 * Cache Configuration 208 */ 209#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ 210 211/* pass open firmware flat tree */ 212#define CONFIG_OF_LIBFDT 1 213#define CONFIG_OF_BOARD_SETUP 1 214 215#endif /* __CONFIG_H */ 216