1/* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de 6 * 7 * TOP5200 differences from IceCube: 8 * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks 9 * bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins 10 * 1 SDRAM/DDRAM Bank up to 256 MB 11 * local VPD I2C Bus is software driven and uses 12 * GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL 13 * FLASH is re-located at 0xff000000 14 * Internal regs are at 0xf0000000 15 * Reset jumps to 0x00000100 16 * 17 * See file CREDITS for list of people who contributed to this 18 * project. 19 * 20 * This program is free software; you can redistribute it and/or 21 * modify it under the terms of the GNU General Public License as 22 * published by the Free Software Foundation; either version 2 of 23 * the License, or (at your option) any later version. 24 * 25 * This program is distributed in the hope that it will be useful, 26 * but WITHOUT ANY WARRANTY; without even the implied warranty of 27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 28 * GNU General Public License for more details. 29 * 30 * You should have received a copy of the GNU General Public License 31 * along with this program; if not, write to the Free Software 32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 33 * MA 02111-1307 USA 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 44#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 45#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ 46#define CONFIG_TOP5200 1 /* ... on TOP5200 board - we need this for FEC.C */ 47 48/* 49 * allowed and functional CONFIG_SYS_TEXT_BASE values: 50 * 0xff000000 low boot at 0x00000100 (default board setting) 51 * 0xfff00000 high boot at 0xfff00100 (board needs modification) 52 * 0x00100000 RAM load and test 53 */ 54#define CONFIG_SYS_TEXT_BASE 0xff000000 55 56#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 57 58#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 59 60/* 61 * Serial console configuration 62 */ 63#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 64#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ 65#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 66 67 68#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) 69/* 70 * PCI Mapping: 71 * 0x40000000 - 0x4fffffff - PCI Memory 72 * 0x50000000 - 0x50ffffff - PCI IO Space 73 */ 74# define CONFIG_PCI 1 75# define CONFIG_PCI_PNP 1 76# define CONFIG_PCI_SCAN_SHOW 1 77# define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 78 79# define CONFIG_PCI_MEM_BUS 0x40000000 80# define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 81# define CONFIG_PCI_MEM_SIZE 0x10000000 82 83# define CONFIG_PCI_IO_BUS 0x50000000 84# define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 85# define CONFIG_PCI_IO_SIZE 0x01000000 86 87#endif 88 89/* USB */ 90#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) 91 92# define CONFIG_USB_OHCI 93# define CONFIG_USB_CLOCK 0x0001bbbb 94# if defined (CONFIG_EVAL5200) 95# define CONFIG_USB_CONFIG 0x00005100 96# else 97# define CONFIG_USB_CONFIG 0x00001000 98# endif 99# define CONFIG_DOS_PARTITION 100# define CONFIG_USB_STORAGE 101 102#endif 103 104/* IDE */ 105#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) 106# define CONFIG_DOS_PARTITION 107#endif 108 109 110/* 111 * BOOTP options 112 */ 113#define CONFIG_BOOTP_BOOTFILESIZE 114#define CONFIG_BOOTP_BOOTPATH 115#define CONFIG_BOOTP_GATEWAY 116#define CONFIG_BOOTP_HOSTNAME 117 118 119/* 120 * Command line configuration. 121 */ 122#include <config_cmd_default.h> 123 124#define CONFIG_CMD_ASKENV 125#define CONFIG_CMD_BEDBUG 126#define CONFIG_CMD_DATE 127#define CONFIG_CMD_DHCP 128#define CONFIG_CMD_EEPROM 129#define CONFIG_CMD_ELF 130#define CONFIG_CMD_I2C 131#define CONFIG_CMD_IMMAP 132#define CONFIG_CMD_MII 133#define CONFIG_CMD_REGINFO 134 135#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) 136#define CONFIG_CMD_FAT 137#define CONFIG_CMD_IDE 138#define CONFIG_CMD_USB 139#define CONFIG_CMD_PCI 140#endif 141 142 143/* 144 * MUST be low boot - HIGHBOOT is not supported anymore 145 */ 146#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ 147# define CONFIG_SYS_LOWBOOT 1 148# define CONFIG_SYS_LOWBOOT16 1 149#else 150# error "CONFIG_SYS_TEXT_BASE must be 0xff000000" 151#endif 152 153/* 154 * Autobooting 155 */ 156#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 157 158#define CONFIG_PREBOOT "echo;" \ 159 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 160 "echo" 161 162#undef CONFIG_BOOTARGS 163 164#define CONFIG_EXTRA_ENV_SETTINGS \ 165 "netdev=eth0\0" \ 166 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 167 "nfsroot=${serverip}:${rootpath}\0" \ 168 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 169 "addip=setenv bootargs ${bootargs} " \ 170 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 171 ":${hostname}:${netdev}:off panic=1\0" \ 172 "flash_nfs=run nfsargs addip;" \ 173 "bootm ${kernel_addr}\0" \ 174 "flash_self=run ramargs addip;" \ 175 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 176 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 177 "rootpath=/opt/eldk/ppc_82xx\0" \ 178 "bootfile=/tftpboot/MPC5200/uImage\0" \ 179 "" 180 181#define CONFIG_BOOTCOMMAND "run flash_self" 182 183/* 184 * IPB Bus clocking configuration. 185 */ 186#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 187 188/* 189 * I2C configuration 190 */ 191/* 192 * EEPROM configuration 193 */ 194#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 195#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 196 197#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 198#define CONFIG_SYS_EEPROM_SIZE 0x2000 199 200#define CONFIG_ENV_OVERWRITE 201#define CONFIG_MISC_INIT_R 202 203#undef CONFIG_HARD_I2C /* I2C with hardware support */ 204#define CONFIG_SOFT_I2C 1 /* I2C with softwate support */ 205 206#if defined (CONFIG_SOFT_I2C) 207# define SDA0 0x40 208# define SCL0 0x80 209# define GPIOE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c00)) 210# define DDR0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c08)) 211# define DVO0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c0c)) 212# define DVI0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c20)) 213# define ODE0 *((volatile uchar*)(CONFIG_SYS_MBAR+0x0c04)) 214# define I2C_INIT {GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);} 215# define I2C_READ ((DVI0&SDA0)?1:0) 216# define I2C_SDA(x) {if(x)DVO0|=SDA0;else DVO0&=~SDA0;} 217# define I2C_SCL(x) {if(x)DVO0|=SCL0;else DVO0&=~SCL0;} 218# define I2C_DELAY {udelay(5);} 219# define I2C_ACTIVE {DDR0|=SDA0;} 220# define I2C_TRISTATE {DDR0&=~SDA0;} 221# define CONFIG_SYS_I2C_SPEED 100000 222# define CONFIG_SYS_I2C_SLAVE 0x7F 223#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 224#define CONFIG_SYS_I2C_FACT_ADDR 0x57 225#endif 226 227#if defined (CONFIG_HARD_I2C) 228# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 229# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 230# define CONFIG_SYS_I2C_SLAVE 0x7F 231#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 232#define CONFIG_SYS_I2C_FACT_ADDR 0x54 233#endif 234 235/* 236 * Flash configuration, expect one 16 Megabyte Bank at most 237 */ 238#define CONFIG_SYS_FLASH_BASE 0xff000000 239#define CONFIG_SYS_FLASH_SIZE 0x01000000 240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 241#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0) 242 243#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 244 245#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 246#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 247 248#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ 249 250/* 251 * DRAM configuration - will be read from VPD later... TODO! 252 */ 253#if 0 254/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */ 255#define CONFIG_SYS_DRAM_DDR 0 256#define CONFIG_SYS_DRAM_EMODE 0 257#define CONFIG_SYS_DRAM_MODE 0x008D 258#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 259#define CONFIG_SYS_DRAM_CONFIG1 0xC2233A00 260#define CONFIG_SYS_DRAM_CONFIG2 0x88B70004 261#define CONFIG_SYS_DRAM_TAP_DEL 0x08 262#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 263#endif 264#if 1 265/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */ 266#define CONFIG_SYS_DRAM_DDR 0 267#define CONFIG_SYS_DRAM_EMODE 0 268#define CONFIG_SYS_DRAM_MODE 0x00CD 269#define CONFIG_SYS_DRAM_CONTROL 0x514F0000 270#define CONFIG_SYS_DRAM_CONFIG1 0xD2333A00 271#define CONFIG_SYS_DRAM_CONFIG2 0x8AD70004 272#define CONFIG_SYS_DRAM_TAP_DEL 0x08 273#define CONFIG_SYS_DRAM_RAM_SIZE 0x19 274#endif 275 276/* 277 * Environment settings 278 */ 279#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */ 280#define CONFIG_ENV_OFFSET 0x1000 281#define CONFIG_ENV_SIZE 0x0700 282 283/* 284 * VPD settings 285 */ 286#define CONFIG_SYS_FACT_OFFSET 0x1800 287#define CONFIG_SYS_FACT_SIZE 0x0800 288 289/* 290 * Memory map 291 * 292 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000 293 */ 294#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */ 295#define CONFIG_SYS_SDRAM_BASE 0x00000000 296#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 297 298/* Use SRAM until RAM will be available */ 299#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 300#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 301 302 303#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 304#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 305 306#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 307#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 308# define CONFIG_SYS_RAMBOOT 1 309#endif 310 311#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 312#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 313#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 314 315/* 316 * Ethernet configuration 317 */ 318#define CONFIG_MPC5xxx_FEC 1 319#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ 320#define CONFIG_PHY_ADDR 0x1f 321#define CONFIG_PHY_TYPE 0x79c874 322/* 323 * GPIO configuration: 324 * PSC1,2,3 predefined as UART 325 * PCI disabled 326 * Ethernet 100 with MD 327 */ 328#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058044 329 330/* 331 * Miscellaneous configurable options 332 */ 333#define CONFIG_SYS_LONGHELP /* undef to save memory */ 334#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 335#if defined(CONFIG_CMD_KGDB) 336# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 337#else 338# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 339#endif 340#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 341#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 342#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 343 344#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 345#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */ 346 347#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ 348 349#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 350 351#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 352#if defined(CONFIG_CMD_KGDB) 353# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 354#endif 355 356 357#ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ 358 #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ 359 #define RTC(reg) (0xf0010000+reg) 360 /* setup CS2 for M48T08. Must MAP 64kB */ 361 #define CONFIG_SYS_CS2_START RTC(0) 362 #define CONFIG_SYS_CS2_SIZE 0x10000 363 /* setup CS2 configuration register: */ 364 /* WaitP = 0, WaitX = 4, MX=0, AL=1, AA=1, CE=1 */ 365 /* AS=2, DS=0, Bank=0, WTyp=0, WS=0, RS=0, WO=0, RO=0 */ 366 #define CONFIG_SYS_CS2_CFG 0x00047800 367#else 368 #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ 369#endif 370 371/* 372 * Various low-level settings 373 */ 374#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 375#define CONFIG_SYS_HID0_FINAL HID0_ICE 376 377#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 378#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 379#define CONFIG_SYS_BOOTCS_CFG 0x00047801 380#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 381#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 382 383#define CONFIG_SYS_CS_BURST 0x00000000 384#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 385 386#define CONFIG_SYS_RESET_ADDRESS 0x7f000000 387 388/*----------------------------------------------------------------------- 389 * IDE/ATA stuff Supports IDE harddisk 390 *----------------------------------------------------------------------- 391 */ 392 393#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 394 395#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 396#undef CONFIG_IDE_LED /* LED for ide not supported */ 397 398#define CONFIG_IDE_RESET 1 399#define CONFIG_IDE_PREINIT 400 401#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 402#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 403 404#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 405 406#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 407 408/* Offset for data I/O */ 409#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 410 411/* Offset for normal register accesses */ 412#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 413 414/* Offset for alternate registers */ 415#define CONFIG_SYS_ATA_ALT_OFFSET (0x005c) 416 417/* Interval between registers */ 418#define CONFIG_SYS_ATA_STRIDE 4 419 420#endif /* __CONFIG_H */ 421