LXR uboot/include/configs/eb

   1/*
   2 * (C) Copyright 2008-2009
   3 * BuS Elektronik GmbH & Co. KG <www.bus-elektronik.de>
   4 * Jens Scharsig <esw@bus-elektronik.de>
   5 *
   6 * Configuation settings for the EB+CPUx9K2 board.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#ifndef _CONFIG_EB_CPUx9K2_H_
  28#define _CONFIG_EB_CPUx9K2_H_
  29
  30/*--------------------------------------------------------------------------*/
  31
  32#define CONFIG_AT91RM9200               /* It's an Atmel AT91RM9200 SoC */
  33#define CONFIG_EB_CPUX9K2               /* on an EP+CPUX9K2 Board       */
  34#define USE_920T_MMU
  35
  36#define CONFIG_VERSION_VARIABLE
  37#define CONFIG_IDENT_STRING     " on EB+CPUx9K2"
  38
  39#include <asm/hardware.h>       /* needed for port definitions */
  40
  41#define CONFIG_MISC_INIT_R
  42#define CONFIG_BOARD_EARLY_INIT_F
  43
  44#define MACH_TYPE_EB_CPUX9K2            1977
  45#define CONFIG_MACH_TYPE                MACH_TYPE_EB_CPUX9K2
  46/*--------------------------------------------------------------------------*/
  47#define CONFIG_SYS_TEXT_BASE            0x00000000
  48#define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
  49
  50#define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
  51#define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
  52#define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
  53
  54
  55#define CONFIG_BOOT_RETRY_TIME          30
  56#define CONFIG_CMDLINE_EDITING
  57
  58#define CONFIG_SYS_PROMPT       "U-Boot> "      /* Monitor Command Prompt */
  59#define CONFIG_SYS_CBSIZE       512             /* Console I/O Buffer Size */
  60#define CONFIG_SYS_MAXARGS      32              /* max number of command args */
  61#define CONFIG_SYS_PBSIZE       \
  62        (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  63
  64#define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
  65
  66/*
  67 * ARM asynchronous clock
  68 */
  69
  70#define AT91C_MAIN_CLOCK        179404800       /* from 12.288 MHz * 73 / 5 */
  71#define AT91C_MASTER_CLOCK      (AT91C_MAIN_CLOCK / 3)
  72#define CONFIG_SYS_HZ           1000
  73#define CONFIG_SYS_HZ_CLOCK     (AT91C_MASTER_CLOCK / 2)
  74
  75#define CONFIG_SYS_AT91_SLOW_CLOCK      32768           /* slow clock */
  76
  77#define CONFIG_CMDLINE_TAG              1
  78#define CONFIG_SETUP_MEMORY_TAGS        1
  79#define CONFIG_INITRD_TAG               1
  80
  81#define CONFIG_SYS_USE_MAIN_OSCILLATOR  1
  82/* flash */
  83#define CONFIG_SYS_EBI_CFGR_VAL         0x00000000
  84#define CONFIG_SYS_SMC_CSR0_VAL         0x00003284 /* 16bit, 2 TDF, 4 WS */
  85
  86/* clocks */
  87#define CONFIG_SYS_PLLAR_VAL            0x20483E05 /* 179.4048 MHz for PCK */
  88#define CONFIG_SYS_PLLBR_VAL            0x104C3E0A /* 47.3088 MHz (for USB) */
  89#define CONFIG_SYS_MCKR_VAL             0x00000202 /* PCK/3 = MCK Clock */
  90
  91/*
  92 * Size of malloc() pool
  93 */
  94
  95#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 520*1024)
  96
  97/*
  98 * sdram
  99 */
 100
 101#define CONFIG_NR_DRAM_BANKS            1
 102
 103#define CONFIG_SYS_SDRAM_BASE           0x20000000
 104#define CONFIG_SYS_SDRAM_SIZE           0x04000000  /* 64 megs */
 105#define CONFIG_SYS_INIT_SP_ADDR         0x00204000  /* use internal SRAM */
 106
 107#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
 108#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 109                                        CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \
 110                                        CONFIG_SYS_MALLOC_LEN)
 111
 112#define CONFIG_SYS_PIOC_ASR_VAL         0xFFFF0000 /* PIOC as D16/D31 */
 113#define CONFIG_SYS_PIOC_BSR_VAL         0x00000000
 114#define CONFIG_SYS_PIOC_PDR_VAL         0xFFFF0000
 115#define CONFIG_SYS_EBI_CSA_VAL          0x00000002 /* CS1=SDRAM */
 116#define CONFIG_SYS_SDRC_CR_VAL          0x2188c159 /* set up the SDRAM */
 117#define CONFIG_SYS_SDRAM                0x20000000 /* address of the SDRAM */
 118#define CONFIG_SYS_SDRAM1               0x20000080 /* address of the SDRAM */
 119#define CONFIG_SYS_SDRAM_VAL            0x00000000 /* value written to SDRAM */
 120#define CONFIG_SYS_SDRC_MR_VAL          0x00000002 /* Precharge All */
 121#define CONFIG_SYS_SDRC_MR_VAL1         0x00000004 /* refresh */
 122#define CONFIG_SYS_SDRC_MR_VAL2         0x00000003 /* Load Mode Register */
 123#define CONFIG_SYS_SDRC_MR_VAL3         0x00000000 /* Normal Mode */
 124#define CONFIG_SYS_SDRC_TR_VAL          0x000002E0 /* Write refresh rate */
 125
 126/*
 127 * Command line configuration
 128 */
 129
 130#include <config_cmd_default.h>
 131
 132#define CONFIG_CMD_BMP
 133#define CONFIG_CMD_DATE
 134#define CONFIG_CMD_DHCP
 135#define CONFIG_CMD_I2C
 136#define CONFIG_CMD_JFFS2
 137#define CONFIG_CMD_MII
 138#define CONFIG_CMD_NAND
 139#define CONFIG_CMD_PING
 140#define CONFIG_I2C_CMD_NO_FLAT
 141#define CONFIG_I2C_CMD_TREE
 142#define CONFIG_CMD_USB
 143#define CONFIG_CMD_FAT
 144
 145#define CONFIG_SYS_LONGHELP
 146
 147/*
 148 * Filesystems
 149 */
 150
 151#define CONFIG_JFFS2_NAND               1
 152
 153#ifndef CONFIG_JFFS2_CMDLINE
 154#define CONFIG_JFFS2_DEV                "nand0"
 155#define CONFIG_JFFS2_PART_OFFSET        0
 156#define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 157#else
 158#define MTDIDS_DEFAULT          "nor0=0,nand0=1"
 159#define MTDPARTS_DEFAULT        "mtdparts="                             \
 160                                        "0:"                            \
 161                                        "384k(U-Boot),"                 \
 162                                        "128k(Env),"                    \
 163                                        "128k(Splash),"                 \
 164                                        "4M(Kernel),"                   \
 165                                        "-(FS)"                         \
 166                                        ";"                             \
 167                                        "1:"                            \
 168                                        "-(jffs2)"
 169#endif /* CONFIG_JFFS2_CMDLINE */
 170
 171/*
 172 * Hardware drivers
 173 */
 174#define CONFIG_USB_ATMEL
 175#define CONFIG_USB_OHCI_NEW
 176#define CONFIG_AT91C_PQFP_UHPBUG
 177#define CONFIG_USB_STORAGE
 178#define CONFIG_DOS_PARTITION
 179#define CONFIG_ISO_PARTITION
 180#define CONFIG_EFI_PARTITION
 181
 182#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      1
 183#define CONFIG_SYS_USB_OHCI_CPU_INIT
 184#define CONFIG_SYS_USB_OHCI_REGS_BASE           0x00300000
 185#define CONFIG_SYS_USB_OHCI_SLOT_NAME           "at91rm9200"
 186
 187/*
 188 * UART/CONSOLE
 189 */
 190
 191#define CONFIG_SYS_BAUDRATE_TABLE       { 115200, 19200, 38400, 57600, 9600 }
 192
 193#define CONFIG_BAUDRATE 115200
 194#define CONFIG_ATMEL_USART
 195#define CONFIG_USART_BASE       ATMEL_BASE_DBGU
 196#define CONFIG_USART_ID         0/* ignored in arm */
 197
 198/*
 199 * network
 200 */
 201
 202#define CONFIG_NET_RETRY_COUNT          10
 203#define CONFIG_RESET_PHY_R              1
 204
 205#define CONFIG_DRIVER_AT91EMAC          1
 206#define CONFIG_DRIVER_AT91EMAC_QUIET    1
 207#define CONFIG_SYS_RX_ETH_BUFFER        8
 208#define CONFIG_MII                      1
 209
 210/*
 211 * BOOTP options
 212 */
 213#define CONFIG_BOOTP_BOOTFILESIZE
 214#define CONFIG_BOOTP_BOOTPATH
 215#define CONFIG_BOOTP_GATEWAY
 216#define CONFIG_BOOTP_HOSTNAME
 217
 218/*
 219 * I2C-Bus
 220 */
 221
 222#define CONFIG_SYS_I2C_SPEED            50000
 223#define CONFIG_SYS_I2C_SLAVE            0               /* not used */
 224
 225#ifndef CONFIG_HARD_I2C
 226#define CONFIG_SOFT_I2C
 227
 228/* Software  I2C driver configuration */
 229
 230#define AT91_PIN_SDA                    (1<<25)         /* AT91C_PIO_PA25 */
 231#define AT91_PIN_SCL                    (1<<26)         /* AT91C_PIO_PA26 */
 232
 233#define CONFIG_SYS_I2C_INIT_BOARD
 234
 235#define I2C_INIT        i2c_init_board();
 236#define I2C_ACTIVE      writel(ATMEL_PMX_AA_TWD, &pio->pioa.mddr);
 237#define I2C_TRISTATE    writel(ATMEL_PMX_AA_TWD, &pio->pioa.mder);
 238#define I2C_READ        ((readl(&pio->pioa.pdsr) & ATMEL_PMX_AA_TWD) != 0)
 239#define I2C_SDA(bit)                                            \
 240        if (bit)                                                \
 241                writel(ATMEL_PMX_AA_TWD, &pio->pioa.sodr);      \
 242        else                                                    \
 243                writel(ATMEL_PMX_AA_TWD, &pio->pioa.codr);
 244#define I2C_SCL(bit)                                            \
 245        if (bit)                                                \
 246                writel(ATMEL_PMX_AA_TWCK, &pio->pioa.sodr);     \
 247        else                                                    \
 248                writel(ATMEL_PMX_AA_TWCK, &pio->pioa.codr);
 249
 250#define I2C_DELAY       udelay(2500000/CONFIG_SYS_I2C_SPEED)
 251
 252#endif  /* CONFIG_HARD_I2C */
 253
 254/* I2C-RTC */
 255
 256#ifdef CONFIG_CMD_DATE
 257#define CONFIG_RTC_DS1338
 258#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 259#endif
 260
 261/* EEPROM */
 262
 263#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 264#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 265
 266/* FLASH organization */
 267
 268/*  NOR-FLASH */
 269#define CONFIG_FLASH_SHOW_PROGRESS      45
 270
 271#define CONFIG_FLASH_CFI_DRIVER 1
 272
 273#define PHYS_FLASH_1                    0x10000000
 274#define PHYS_FLASH_SIZE                 0x01000000  /* 16 megs main flash */
 275#define CONFIG_SYS_FLASH_CFI            1
 276#define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 277
 278#define CONFIG_SYS_FLASH_PROTECTION     1
 279#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 280#define CONFIG_SYS_MAX_FLASH_BANKS      1
 281#define CONFIG_SYS_MAX_FLASH_SECT       512
 282#define CONFIG_SYS_FLASH_ERASE_TOUT     6000
 283#define CONFIG_SYS_FLASH_WRITE_TOUT     2000
 284
 285/* NAND */
 286
 287#define CONFIG_SYS_MAX_NAND_DEVICE      1
 288#define CONFIG_SYS_NAND_BASE            0x40000000
 289#define CONFIG_SYS_NAND_DBW_8           1
 290
 291#define CONFIG_SYS_64BIT_VSPRINTF       1
 292
 293/* Status LED's */
 294
 295#define CONFIG_STATUS_LED               1
 296#define CONFIG_BOARD_SPECIFIC_LED       1
 297
 298#define STATUS_LED_BOOT                 1
 299#define STATUS_LED_ACTIVE               0
 300
 301#define STATUS_LED_BIT                  1       /* AT91C_PIO_PD0 green LED */
 302#define STATUS_LED_PERIOD               (CONFIG_SYS_HZ / 2)
 303#define STATUS_LED_STATE                STATUS_LED_OFF          /* BLINKING */
 304#define STATUS_LED_BIT1                 2       /* AT91C_PIO_PD1  red LED */
 305#define STATUS_LED_STATE1               STATUS_LED_ON           /* BLINKING */
 306#define STATUS_LED_PERIOD1              (CONFIG_SYS_HZ / 4)
 307
 308#define CONFIG_VIDEO                    1
 309
 310/* Options */
 311
 312#ifdef CONFIG_VIDEO
 313
 314#define CONFIG_VIDEO_VCXK                       1
 315
 316#define CONFIG_SPLASH_SCREEN                    1
 317
 318#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN       4
 319#define CONFIG_SYS_VCXK_BASE    0x30000000
 320
 321#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN         (1<<3)
 322#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT        piob
 323#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR         odr
 324
 325#define CONFIG_SYS_VCXK_ENABLE_PIN              (1<<5)
 326#define CONFIG_SYS_VCXK_ENABLE_PORT             piob
 327#define CONFIG_SYS_VCXK_ENABLE_DDR              oer
 328
 329#define CONFIG_SYS_VCXK_REQUEST_PIN             (1<<2)
 330#define CONFIG_SYS_VCXK_REQUEST_PORT            piob
 331#define CONFIG_SYS_VCXK_REQUEST_DDR             oer
 332
 333#define CONFIG_SYS_VCXK_INVERT_PIN              (1<<4)
 334#define CONFIG_SYS_VCXK_INVERT_PORT             piob
 335#define CONFIG_SYS_VCXK_INVERT_DDR              oer
 336
 337#define CONFIG_SYS_VCXK_RESET_PIN               (1<<6)
 338#define CONFIG_SYS_VCXK_RESET_PORT              piob
 339#define CONFIG_SYS_VCXK_RESET_DDR               oer
 340
 341#endif  /* CONFIG_VIDEO */
 342
 343/* Environment */
 344
 345#define CONFIG_BOOTDELAY                5
 346
 347#define CONFIG_ENV_IS_IN_FLASH          1
 348#define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)
 349#define CONFIG_ENV_SIZE                 0x20000 /* sectors are 128K here */
 350
 351#define CONFIG_BAUDRATE                 115200
 352
 353#define CONFIG_BOOTCOMMAND              "run nfsboot"
 354
 355#define CONFIG_NFSBOOTCOMMAND                                           \
 356                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 357                "run bootargsdefaults;"                                 \
 358                "set bootargs $(bootargs) boot=nfs "                    \
 359                ";echo $(bootargs)"                                     \
 360        ";bootm"
 361
 362#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 363        "displaywidth=256\0"                                            \
 364        "displayheight=512\0"                                           \
 365        "displaybsteps=1023\0"                                          \
 366        "ubootaddr=10000000\0"                                          \
 367        "splashimage=10080000\0"                                        \
 368        "kerneladdr=100A0000\0"                                         \
 369        "kernelsize=00400000\0"                                         \
 370        "rootfsaddr=104A0000\0"                                         \
 371        "copy_addr=21200000\0"                                          \
 372        "rootfssize=00B60000\0"                                         \
 373        "bootargsdefaults=set bootargs "                                \
 374                "console=ttyS0,115200 "                                 \
 375                "video=vcxk_fb:xres:${displaywidth},"                   \
 376                        "yres:${displayheight},"                        \
 377                        "bres:${displaybsteps} "                        \
 378                "mem=62M "                                              \
 379                "panic=10 "                                             \
 380                "uboot=\\\"${ver}\\\" "                                 \
 381                "\0"                                                    \
 382        "update_kernel=protect off $(kerneladdr) +$(kernelsize);"       \
 383                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 384                "erase $(kerneladdr) +$(kernelsize);"                   \
 385                "cp.b $(fileaddr) $(kerneladdr) $(filesize);"           \
 386                "protect on $(kerneladdr) +$(kernelsize)"               \
 387                "\0"                                                    \
 388        "update_root=protect off $(rootfsaddr) +$(rootfssize);"         \
 389                "dhcp $(copy_addr) rfs;"                                \
 390                "erase $(rootfsaddr) +$(rootfssize);"                   \
 391                "cp.b $(fileaddr) $(rootfsaddr) $(filesize);"           \
 392                "\0"                                                    \
 393        "update_uboot=protect off 10000000 1005FFFF;"                   \
 394                "dhcp $(copy_addr) u-boot_eb_cpux9k2;"                  \
 395                "erase 10000000 1005FFFF;"                              \
 396                "cp.b $(fileaddr) $(ubootaddr) $(filesize);"            \
 397                "protect on 10000000 1005FFFF;reset\0"                  \
 398        "update_splash=protect off $(splashimage) +20000;"              \
 399                "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;"              \
 400                "erase $(splashimage) +20000;"                          \
 401                "cp.b $(fileaddr) 10080000 $(filesize);"                \
 402                "protect on $(splashimage) +20000;reset\0"              \
 403        "emergency=run bootargsdefaults;"                               \
 404                "set bootargs $(bootargs) root=initramfs boot=emergency " \
 405                ";bootm $(kerneladdr)\0"                                \
 406        "netemergency=run bootargsdefaults;"                            \
 407                "dhcp $(copy_addr) uImage_cpux9k2;"                     \
 408                "set bootargs $(bootargs) root=initramfs boot=emergency " \
 409                ";bootm $(copy_addr)\0"                                 \
 410        "norboot=run bootargsdefaults;"                                 \
 411                "set bootargs $(bootargs) root=initramfs boot=local "   \
 412                ";bootm $(kerneladdr)\0"                                \
 413        "nandboot=run bootargsdefaults;"                                \
 414                "set bootargs $(bootargs) root=initramfs boot=nand "    \
 415                ";bootm $(kerneladdr)\0"                                \
 416        " "
 417
 418/*--------------------------------------------------------------------------*/
 419
 420#endif
 421
 422/* EOF */
 423