1/* 2 * 3 * BRIEF MODULE DESCRIPTION 4 * OMAP730 hardware map 5 * 6 * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk) 7 * Author: MPC-Data Limited 8 * Dave Peverley 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 * 15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * You should have received a copy of the GNU General Public License along 27 * with this program; if not, write to the Free Software Foundation, Inc., 28 * 675 Mass Ave, Cambridge, MA 02139, USA. 29 */ 30 31#ifndef __INCLUDED_OMAP730_H 32#define __INCLUDED_OMAP730_H 33 34#include <asm/sizes.h> 35 36/*************************************************************************** 37 * OMAP730 Configuration Registers 38 **************************************************************************/ 39 40#define PERSEUS2_MPU_DEV_ID ((unsigned int)(0xFFFE1000)) 41#define PERSEUS2_GSM_DEV_ID0 ((unsigned int)(0xFFFE1000)) 42#define PERSEUS2_GDM_DEV_ID1 ((unsigned int)(0xFFFE1002)) 43#define DSP_CONF ((unsigned int)(0xFFFE1004)) 44#define PERSEUS2_MPU_DIE_ID0 ((unsigned int)(0xFFFE1008)) 45#define GSM_ASIC_CONF ((unsigned int)(0xFFFE1008)) 46#define PERSEUS2_MPU_DIE_ID1 ((unsigned int)(0xFFFE100C)) 47#define PERSEUS2_MODE1 ((unsigned int)(0xFFFE1010)) 48#define PERSEUS2_GSM_DIE_ID0 ((unsigned int)(0xFFFE1010)) 49#define PERSEUS2_GSM_DIE_ID1 ((unsigned int)(0xFFFE1012)) 50#define PERSEUS2_MODE2 ((unsigned int)(0xFFFE1014)) 51#define PERSEUS2_GSM_DIE_ID2 ((unsigned int)(0xFFFE1014)) 52#define PERSEUS2_GSM_DIE_ID3 ((unsigned int)(0xFFFE1016)) 53#define PERSEUS2_ANALOG_CELLS_CONF ((unsigned int)(0xFFFE1018)) 54#define SPECCTL ((unsigned int)(0xFFFE101C)) 55#define SPARE1 ((unsigned int)(0xFFFE1020)) 56#define SPARE2 ((unsigned int)(0xFFFE1024)) 57#define GSM_PBG_IRQ ((unsigned int)(0xFFFE1028)) 58#define DMA_REQ_CONF ((unsigned int)(0xFFFE1030)) 59#define PE_CONF_NO_DUAL ((unsigned int)(0xFFFE1060)) 60#define PERSEUS2_IO_CONF0 ((unsigned int)(0xFFFE1070)) 61#define PERSEUS2_IO_CONF1 ((unsigned int)(0xFFFE1074)) 62#define PERSEUS2_IO_CONF2 ((unsigned int)(0xFFFE1078)) 63#define PERSEUS2_IO_CONF3 ((unsigned int)(0xFFFE107C)) 64#define PERSEUS2_IO_CONF4 ((unsigned int)(0xFFFE1080)) 65#define PERSEUS2_IO_CONF5 ((unsigned int)(0xFFFE1084)) 66#define PERSEUS2_IO_CONF6 ((unsigned int)(0xFFFE1088)) 67#define PERSEUS2_IO_CONF7 ((unsigned int)(0xFFFE108C)) 68#define PERSEUS2_IO_CONF8 ((unsigned int)(0xFFFE1090)) 69#define PERSEUS2_IO_CONF9 ((unsigned int)(0xFFFE1094)) 70#define PERSEUS2_IO_CONF10 ((unsigned int)(0xFFFE1098)) 71#define PERSEUS2_IO_CONF11 ((unsigned int)(0xFFFE109C)) 72#define PERSEUS2_IO_CONF12 ((unsigned int)(0xFFFE10A0)) 73#define PERSEUS2_IO_CONF13 ((unsigned int)(0xFFFE10A4)) 74#define PERSEUS_PCC_CONF_REG ((unsigned int)(0xFFFE10B4)) 75#define BIST_STATUS_INTERNAL ((unsigned int)(0xFFFE10B8)) 76#define BIST_CONTROL ((unsigned int)(0xFFFE10C0)) 77#define BOOT_ROM_REG ((unsigned int)(0xFFFE10C4)) 78#define PRODUCTION_ID_REG ((unsigned int)(0xFFFE10C8)) 79#define BIST_SECROM_SIGNATURE1_INTERNAL ((unsigned int)(0xFFFE10D0)) 80#define BIST_SECROM_SIGNATURE2_INTERNAL ((unsigned int)(0xFFFE10D4)) 81#define BIST_CONTROL_2 ((unsigned int)(0xFFFE10D8)) 82#define DEBUG1 ((unsigned int)(0xFFFE10E0)) 83#define DEBUG2 ((unsigned int)(0xFFFE10E4)) 84#define DEBUG_DMA_IRQ ((unsigned int)(0xFFFE10E8)) 85 86/*************************************************************************** 87 * OMAP730 EMIFS Registers (TRM 2.5.7) 88 **************************************************************************/ 89 90#define TCMIF_BASE 0xFFFECC00 91 92#define EMIFS_LRUREG (TCMIF_BASE + 0x04) 93#define EMIFS_CONFIG (TCMIF_BASE + 0x0C) 94#define FLASH_CFG_0 (TCMIF_BASE + 0x10) 95#define FLASH_CFG_1 (TCMIF_BASE + 0x14) 96#define FLASH_CFG_2 (TCMIF_BASE + 0x18) 97#define FLASH_CFG_3 (TCMIF_BASE + 0x1C) 98#define FL_CFG_DYN_WAIT (TCMIF_BASE + 0x40) 99#define EMIFS_TIMEOUT1_REG (TCMIF_BASE + 0x28) 100#define EMIFS_TIMEOUT2_REG (TCMIF_BASE + 0x2C) 101#define EMIFS_TIMEOUT3_REG (TCMIF_BASE + 0x30) 102#define EMIFS_ABORT_ADDR (TCMIF_BASE + 0x44) 103#define EMIFS_ABORT_TYPE (TCMIF_BASE + 0x48) 104#define EMIFS_ABORT_TOUT (TCMIF_BASE + 0x4C) 105#define FLASH_ACFG_0_1 (TCMIF_BASE + 0x50) 106#define FLASH_ACFG_1_1 (TCMIF_BASE + 0x54) 107#define FLASH_ACFG_2_1 (TCMIF_BASE + 0x58) 108#define FLASH_ACFG_3_1 (TCMIF_BASE + 0x5C) 109 110/*************************************************************************** 111 * OMAP730 Interrupt handlers 112 **************************************************************************/ 113 114#define OMAP_IH1_BASE 0xFFFECB00 /* MPU Level 1 IRQ handler */ 115#define OMAP_IH2_BASE 0xfffe0000 116 117/*************************************************************************** 118 * OMAP730 Timers 119 * 120 * There are three general purpose OS timers in the 730 that can be 121 * configured in autoreload or one-shot modes. 122 **************************************************************************/ 123 124#define OMAP730_32kHz_TIMER_BASE 0xFFFB9000 125 126/* 32k Timer Registers */ 127#define TIMER32k_CR 0x08 128#define TIMER32k_TVR 0x00 129#define TIMER32k_TCR 0x04 130 131/* 32k Timer Control Register definition */ 132#define TIMER32k_TSS (1<<0) 133#define TIMER32k_TRB (1<<1) 134#define TIMER32k_INT (1<<2) 135#define TIMER32k_ARL (1<<3) 136 137/* MPU Timer base addresses */ 138#define OMAP730_MPUTIMER_BASE 0xfffec500 139#define OMAP730_MPUTIMER_OFF 0x00000100 140 141#define OMAP730_TIMER1_BASE 0xFFFEC500 142#define OMAP730_TIMER2_BASE 0xFFFEC600 143#define OMAP730_TIMER3_BASE 0xFFFEC700 144 145/* MPU Timer Register offsets */ 146#define CNTL_TIMER 0x00 /* MPU_CNTL_TIMER */ 147#define LOAD_TIM 0x04 /* MPU_LOAD_TIMER */ 148#define READ_TIM 0x08 /* MPU_READ_TIMER */ 149 150/* MPU_CNTL_TIMER register bits */ 151#define MPUTIM_FREE (1<<6) 152#define MPUTIM_CLOCK_ENABLE (1<<5) 153#define MPUTIM_PTV_MASK (0x7<<MPUTIM_PTV_BIT) 154#define MPUTIM_PTV_BIT 2 155#define MPUTIM_AR (1<<1) 156#define MPUTIM_ST (1<<0) 157 158/*************************************************************************** 159 * OMAP730 GPIO 160 * 161 * The GPIO control is split over 6 register bases in the OMAP730 to allow 162 * access to all the (6 x 32) GPIO pins! 163 **************************************************************************/ 164 165#define OMAP730_GPIO_BASE_1 0xFFFBC000 166#define OMAP730_GPIO_BASE_2 0xFFFBC800 167#define OMAP730_GPIO_BASE_3 0xFFFBD000 168#define OMAP730_GPIO_BASE_4 0xFFFBD800 169#define OMAP730_GPIO_BASE_5 0xFFFBE000 170#define OMAP730_GPIO_BASE_6 0xFFFBE800 171 172#define GPIO_DATA_INPUT 0x00 173#define GPIO_DATA_OUTPUT 0x04 174#define GPIO_DIRECTION_CONTROL 0x08 175#define GPIO_INTERRUPT_CONTROL 0x0C 176#define GPIO_INTERRUPT_MASK 0x10 177#define GPIO_INTERRUPT_STATUS 0x14 178 179#define GPIO_DATA_INPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT)) 180#define GPIO_DATA_OUTPUT_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT)) 181#define GPIO_DIRECTION_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL)) 182#define GPIO_INTERRUPT_CONTROL_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL)) 183#define GPIO_INTERRUPT_MASK_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK)) 184#define GPIO_INTERRUPT_STATUS_1 ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS)) 185 186#define GPIO_DATA_INPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT)) 187#define GPIO_DATA_OUTPUT_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT)) 188#define GPIO_DIRECTION_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL)) 189#define GPIO_INTERRUPT_CONTROL_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL)) 190#define GPIO_INTERRUPT_MASK_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK)) 191#define GPIO_INTERRUPT_STATUS_2 ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS)) 192 193#define GPIO_DATA_INPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT)) 194#define GPIO_DATA_OUTPUT_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT)) 195#define GPIO_DIRECTION_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL)) 196#define GPIO_INTERRUPT_CONTROL_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL)) 197#define GPIO_INTERRUPT_MASK_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK)) 198#define GPIO_INTERRUPT_STATUS_3 ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS)) 199 200#define GPIO_DATA_INPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT)) 201#define GPIO_DATA_OUTPUT_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT)) 202#define GPIO_DIRECTION_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL)) 203#define GPIO_INTERRUPT_CONTROL_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL)) 204#define GPIO_INTERRUPT_MASK_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK)) 205#define GPIO_INTERRUPT_STATUS_4 ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS)) 206 207#define GPIO_DATA_INPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT)) 208#define GPIO_DATA_OUTPUT_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT)) 209#define GPIO_DIRECTION_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL)) 210#define GPIO_INTERRUPT_CONTROL_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL)) 211#define GPIO_INTERRUPT_MASK_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK)) 212#define GPIO_INTERRUPT_STATUS_5 ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS)) 213 214#define GPIO_DATA_INPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT)) 215#define GPIO_DATA_OUTPUT_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT)) 216#define GPIO_DIRECTION_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL)) 217#define GPIO_INTERRUPT_CONTROL_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL)) 218#define GPIO_INTERRUPT_MASK_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK)) 219#define GPIO_INTERRUPT_STATUS_6 ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS)) 220 221/*************************************************************************** 222 * OMAP730 Watchdog timers 223 **************************************************************************/ 224 225#define WDTIM_BASE 0xFFFEC800 226#define WDTIM_CONTROL (WDTIM_BASE + 0x00) /* MPU_CNTL_TIMER */ 227#define WDTIM_LOAD (WDTIM_BASE + 0x04) /* MPU_LOAD_TIMER */ 228#define WDTIM_READ (WDTIM_BASE + 0x04) /* MPU_READ_TIMER */ 229#define WDTIM_MODE (WDTIM_BASE + 0x08) /* MPU_TIMER_MODE */ 230 231/*************************************************************************** 232 * OMAP730 Interrupt Registers 233 **************************************************************************/ 234 235/* Interrupt Register offsets */ 236 237#define IRQ_ITR 0x00 238#define IRQ_MIR 0x04 239#define IRQ_SIR_IRQ 0x10 240#define IRQ_SIR_FIQ 0x14 241#define IRQ_CONTROL_REG 0x18 242#define IRQ_ILR0 0x1C /* ILRx == ILR0 + (0x4 * x) */ 243#define IRQ_SIR 0x9C /* a.k.a.IRQ_ISR */ 244#define IRQ_GMIR 0xA0 245 246#define REG_IHL1_MIR (OMAP_IH1_BASE + IRQ_MIR) 247#define REG_IHL2_MIR (OMAP_IH2_BASE + IRQ_MIR) 248 249/*************************************************************************** 250 * OMAP730 Intersystem Communication Register (TRM 4.5) 251 **************************************************************************/ 252 253#define ICR_BASE 0xFFFBB800 254 255#define M_ICR (ICR_BASE + 0x00) 256#define G_ICR (ICR_BASE + 0x02) 257#define M_CTL (ICR_BASE + 0x04) 258#define G_CTL (ICR_BASE + 0x06) 259#define PM_BA (ICR_BASE + 0x0A) 260#define DM_BA (ICR_BASE + 0x0C) 261#define RM_BA (ICR_BASE + 0x0E) 262#define SSPI_TAS (ICR_BASE + 0x12) 263 264#endif /* ! __INCLUDED_OMAP730_H */ 265