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24#include <common.h>
25#include <asm/io.h>
26#include <asm-generic/gpio.h>
27#include <asm/arch/tegra2.h>
28#include <asm/arch/clk_rst.h>
29#include <asm/arch/clock.h>
30#include <asm/arch/gpio.h>
31#include <asm/arch/pinmux.h>
32#include <asm/arch/sys_proto.h>
33#include <asm/arch/uart.h>
34#include <asm/arch/usb.h>
35#include <libfdt.h>
36#include <fdtdec.h>
37
38enum {
39 USB_PORTS_MAX = 4,
40};
41
42
43enum {
44 PARAM_DIVN,
45 PARAM_DIVM,
46 PARAM_DIVP,
47 PARAM_CPCON,
48 PARAM_LFCON,
49 PARAM_ENABLE_DELAY_COUNT,
50 PARAM_STABLE_COUNT,
51 PARAM_ACTIVE_DELAY_COUNT,
52 PARAM_XTAL_FREQ_COUNT,
53 PARAM_DEBOUNCE_A_TIME,
54 PARAM_BIAS_TIME,
55
56 PARAM_COUNT
57};
58
59
60enum dr_mode {
61 DR_MODE_NONE = 0,
62 DR_MODE_HOST,
63 DR_MODE_DEVICE,
64 DR_MODE_OTG,
65};
66
67
68struct fdt_usb {
69 struct usb_ctlr *reg;
70 unsigned utmi:1;
71 unsigned enabled:1;
72 unsigned has_legacy_mode:1;
73 enum dr_mode dr_mode;
74 enum periph_id periph_id;
75 struct fdt_gpio_state vbus_gpio;
76};
77
78static struct fdt_usb port[USB_PORTS_MAX];
79static unsigned port_count;
80static int port_current;
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122
123static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
124
125 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
126 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
127 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
128 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
129};
130
131
132static const u8 utmip_idle_wait_delay = 17;
133
134
135static const u8 utmip_elastic_limit = 16;
136
137
138static const u8 utmip_hs_sync_start_delay = 9;
139
140
141static void set_host_mode(struct fdt_usb *config)
142{
143 if (config->dr_mode == DR_MODE_OTG) {
144
145 if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)
146 return;
147
148
149
150
151
152 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
153 fdtdec_setup_gpio(&config->vbus_gpio);
154 gpio_direction_output(config->vbus_gpio.gpio, 1);
155 debug("set_host_mode: GPIO %d high\n",
156 config->vbus_gpio.gpio);
157 }
158 }
159}
160
161void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
162{
163
164 reset_periph(config->periph_id, 2);
165
166
167
168
169
170 if (config->has_legacy_mode)
171 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
172
173
174 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
175
176
177 if (config->utmi)
178 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
179
180
181
182
183
184}
185
186
187static int init_usb_controller(struct fdt_usb *config,
188 struct usb_ctlr *usbctlr, const u32 timing[])
189{
190 u32 val;
191 int loop_count;
192
193 clock_enable(config->periph_id);
194
195
196 usbf_reset_controller(config, usbctlr);
197
198
199 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
200
201
202 udelay(1);
203
204
205
206
207
208 if (fdt_gpio_isvalid(&config->vbus_gpio)) {
209 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
210 VBUS_SENSE_CTL_MASK,
211 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
212 }
213
214
215
216
217
218 val = readl(&usbctlr->utmip_misc_cfg1);
219 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
220 timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
221 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
222 timing[PARAM_ACTIVE_DELAY_COUNT] <<
223 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
224 writel(val, &usbctlr->utmip_misc_cfg1);
225
226
227 val = readl(&usbctlr->utmip_pll_cfg1);
228 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
229 timing[PARAM_ENABLE_DELAY_COUNT] <<
230 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
231 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
232 timing[PARAM_XTAL_FREQ_COUNT] <<
233 UTMIP_XTAL_FREQ_COUNT_SHIFT);
234 writel(val, &usbctlr->utmip_pll_cfg1);
235
236
237 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
238 UTMIP_BIAS_PDTRK_COUNT_MASK,
239 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
240
241
242 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
243 UTMIP_DEBOUNCE_CFG0_MASK,
244 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
245
246 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
247
248
249 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
250
251 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
252 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
253
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263
264 val = readl(&usbctlr->utmip_hsrx_cfg0);
265 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
266 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
267 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
268 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
269 writel(val, &usbctlr->utmip_hsrx_cfg0);
270
271
272 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
273 UTMIP_HS_SYNC_START_DLY_MASK,
274 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
275
276
277 udelay(1);
278
279
280 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
281
282
283
284
285 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
286
287
288 for (loop_count = 100000; loop_count != 0; loop_count--) {
289 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
290 break;
291 udelay(1);
292 }
293 if (loop_count == 100000)
294 return -1;
295
296 return 0;
297}
298
299static void power_up_port(struct usb_ctlr *usbctlr)
300{
301
302 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
303 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
304 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
305 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
306}
307
308static void config_clock(const u32 timing[])
309{
310 clock_start_pll(CLOCK_ID_USB,
311 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
312 timing[PARAM_CPCON], timing[PARAM_LFCON]);
313}
314
315
316
317
318
319
320
321static int add_port(struct fdt_usb *config, const u32 timing[])
322{
323 struct usb_ctlr *usbctlr = config->reg;
324
325 if (port_count == USB_PORTS_MAX) {
326 debug("tegrausb: Cannot register more than %d ports\n",
327 USB_PORTS_MAX);
328 return -1;
329 }
330 if (init_usb_controller(config, usbctlr, timing)) {
331 debug("tegrausb: Cannot init port\n");
332 return -1;
333 }
334 if (config->utmi) {
335
336 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
337
338
339 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
340 PTS_UTMI << PTS_SHIFT);
341 clrbits_le32(&usbctlr->port_sc1, STS);
342 power_up_port(usbctlr);
343 }
344 port[port_count++] = *config;
345
346 return 0;
347}
348
349int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
350{
351 struct usb_ctlr *usbctlr;
352
353 if (portnum >= port_count)
354 return -1;
355 tegrausb_stop_port();
356 set_host_mode(&port[portnum]);
357
358 usbctlr = port[portnum].reg;
359 *hccr = (u32)&usbctlr->cap_length;
360 *hcor = (u32)&usbctlr->usb_cmd;
361 port_current = portnum;
362 return 0;
363}
364
365int tegrausb_stop_port(void)
366{
367 struct usb_ctlr *usbctlr;
368
369 if (port_current == -1)
370 return -1;
371
372 usbctlr = port[port_current].reg;
373
374
375 writel(0, &usbctlr->usb_cmd);
376 udelay(1000);
377
378
379 writel(2, &usbctlr->usb_cmd);
380 udelay(1000);
381 port_current = -1;
382 return 0;
383}
384
385int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
386 struct fdt_usb *config)
387{
388 const char *phy, *mode;
389
390 config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
391 mode = fdt_getprop(blob, node, "dr_mode", NULL);
392 if (mode) {
393 if (0 == strcmp(mode, "host"))
394 config->dr_mode = DR_MODE_HOST;
395 else if (0 == strcmp(mode, "peripheral"))
396 config->dr_mode = DR_MODE_DEVICE;
397 else if (0 == strcmp(mode, "otg"))
398 config->dr_mode = DR_MODE_OTG;
399 else {
400 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
401 mode);
402 return -FDT_ERR_NOTFOUND;
403 }
404 } else {
405 config->dr_mode = DR_MODE_HOST;
406 }
407
408 phy = fdt_getprop(blob, node, "phy_type", NULL);
409 config->utmi = phy && 0 == strcmp("utmi", phy);
410 config->enabled = fdtdec_get_is_enabled(blob, node);
411 config->has_legacy_mode = fdtdec_get_bool(blob, node,
412 "nvidia,has-legacy-mode");
413 config->periph_id = clock_decode_periph_id(blob, node);
414 if (config->periph_id == PERIPH_ID_NONE) {
415 debug("%s: Missing/invalid peripheral ID\n", __func__);
416 return -FDT_ERR_NOTFOUND;
417 }
418 fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
419 debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
420 "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
421 config->utmi, config->periph_id, config->vbus_gpio.gpio,
422 config->dr_mode);
423
424 return 0;
425}
426
427int board_usb_init(const void *blob)
428{
429 struct fdt_usb config;
430 unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
431 enum clock_osc_freq freq;
432 int node_list[USB_PORTS_MAX];
433 int node, count, i;
434
435
436 freq = clock_get_osc_freq();
437 config_clock(usb_pll[freq]);
438
439
440 count = fdtdec_find_aliases_for_id(blob, "usb",
441 COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
442 for (i = 0; i < count; i++) {
443 debug("USB %d: ", i);
444 node = node_list[i];
445 if (!node)
446 continue;
447 if (fdt_decode_usb(blob, node, osc_freq, &config)) {
448 debug("Cannot decode USB node %s\n",
449 fdt_get_name(blob, node, NULL));
450 return -1;
451 }
452
453 if (add_port(&config, usb_pll[freq]))
454 return -1;
455 set_host_mode(&config);
456 }
457 port_current = -1;
458
459 return 0;
460}
461