LXR uboot/arch/arm/cpu/pxa/usb.c

   1/*
   2 * (C) Copyright 2006
   3 * Markus Klotzbuecher, DENX Software Engineering <mk@denx.de>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25
  26#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
  27# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
  28
  29#include <asm/arch/pxa-regs.h>
  30#include <asm/io.h>
  31#include <usb.h>
  32
  33int usb_cpu_init(void)
  34{
  35#if defined(CONFIG_CPU_MONAHANS)
  36        /* Enable USB host clock. */
  37        writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
  38        udelay(100);
  39#endif
  40#if defined(CONFIG_CPU_PXA27X)
  41        /* Enable USB host clock. */
  42        writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
  43#endif
  44
  45#if defined(CONFIG_CPU_MONAHANS)
  46        /* Configure Port 2 for Host (USB Client Registers) */
  47        writel(0x3000c, UP2OCR);
  48#endif
  49
  50        writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  51        mdelay(11);
  52        writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  53
  54        writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  55        while (readl(UHCHR) & UHCHR_FSBIR)
  56                udelay(1);
  57
  58#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
  59        writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
  60#endif
  61#if defined(CONFIG_CPU_PXA27X)
  62        writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
  63#endif
  64        writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
  65
  66        return 0;
  67}
  68
  69int usb_cpu_stop(void)
  70{
  71        writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
  72        udelay(11);
  73        writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
  74
  75        writel(readl(UHCCOMS) | UHCCOMS_HCR, UHCCOMS);
  76        udelay(10);
  77
  78#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
  79        writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
  80#endif
  81#if defined(CONFIG_CPU_PXA27X)
  82        writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
  83#endif
  84        writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
  85
  86#if defined(CONFIG_CPU_MONAHANS)
  87        /* Disable USB host clock. */
  88        writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
  89        udelay(100);
  90#endif
  91#if defined(CONFIG_CPU_PXA27X)
  92        /* Disable USB host clock. */
  93        writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
  94#endif
  95
  96        return 0;
  97}
  98
  99int usb_cpu_init_fail(void)
 100{
 101        return usb_cpu_stop();
 102}
 103
 104# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
 105#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
 106