1/* 2 * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9_smc.h] 3 * 4 * Copyright (C) 2007 Andrew Victor 5 * Copyright (C) 2007 Atmel Corporation. 6 * 7 * Static Memory Controllers (SMC) - System peripherals registers. 8 * Based on AT91SAM9261 datasheet revision D. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 */ 15 16#ifndef AT91SAM9_SMC_H 17#define AT91SAM9_SMC_H 18 19#ifdef __ASSEMBLY__ 20 21#ifndef ATMEL_BASE_SMC 22#define ATMEL_BASE_SMC ATMEL_BASE_SMC0 23#endif 24 25#define AT91_ASM_SMC_SETUP0 ATMEL_BASE_SMC 26#define AT91_ASM_SMC_PULSE0 (ATMEL_BASE_SMC + 0x04) 27#define AT91_ASM_SMC_CYCLE0 (ATMEL_BASE_SMC + 0x08) 28#define AT91_ASM_SMC_MODE0 (ATMEL_BASE_SMC + 0x0C) 29 30#else 31 32typedef struct at91_cs { 33 u32 setup; /* 0x00 SMC Setup Register */ 34 u32 pulse; /* 0x04 SMC Pulse Register */ 35 u32 cycle; /* 0x08 SMC Cycle Register */ 36 u32 mode; /* 0x0C SMC Mode Register */ 37} at91_cs_t; 38 39typedef struct at91_smc { 40 at91_cs_t cs[8]; 41} at91_smc_t; 42 43#endif /* __ASSEMBLY__ */ 44 45#define AT91_SMC_SETUP_NWE(x) (x & 0x3f) 46#define AT91_SMC_SETUP_NCS_WR(x) ((x & 0x3f) << 8) 47#define AT91_SMC_SETUP_NRD(x) ((x & 0x3f) << 16) 48#define AT91_SMC_SETUP_NCS_RD(x) ((x & 0x3f) << 24) 49 50#define AT91_SMC_PULSE_NWE(x) (x & 0x7f) 51#define AT91_SMC_PULSE_NCS_WR(x) ((x & 0x7f) << 8) 52#define AT91_SMC_PULSE_NRD(x) ((x & 0x7f) << 16) 53#define AT91_SMC_PULSE_NCS_RD(x) ((x & 0x7f) << 24) 54 55#define AT91_SMC_CYCLE_NWE(x) (x & 0x1ff) 56#define AT91_SMC_CYCLE_NRD(x) ((x & 0x1ff) << 16) 57 58#define AT91_SMC_MODE_RM_NCS 0x00000000 59#define AT91_SMC_MODE_RM_NRD 0x00000001 60#define AT91_SMC_MODE_WM_NCS 0x00000000 61#define AT91_SMC_MODE_WM_NWE 0x00000002 62 63#define AT91_SMC_MODE_EXNW_DISABLE 0x00000000 64#define AT91_SMC_MODE_EXNW_FROZEN 0x00000020 65#define AT91_SMC_MODE_EXNW_READY 0x00000030 66 67#define AT91_SMC_MODE_BAT 0x00000100 68#define AT91_SMC_MODE_DBW_8 0x00000000 69#define AT91_SMC_MODE_DBW_16 0x00001000 70#define AT91_SMC_MODE_DBW_32 0x00002000 71#define AT91_SMC_MODE_TDF_CYCLE(x) ((x & 0xf) << 16) 72#define AT91_SMC_MODE_TDF 0x00100000 73#define AT91_SMC_MODE_PMEN 0x01000000 74#define AT91_SMC_MODE_PS_4 0x00000000 75#define AT91_SMC_MODE_PS_8 0x10000000 76#define AT91_SMC_MODE_PS_16 0x20000000 77#define AT91_SMC_MODE_PS_32 0x30000000 78 79#ifdef CONFIG_AT91_LEGACY 80 81#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 82#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ 83#define AT91_SMC_NWESETUP_(x) ((x) << 0) 84#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ 85#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) 86#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ 87#define AT91_SMC_NRDSETUP_(x) ((x) << 16) 88#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ 89#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) 90 91#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 92#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ 93#define AT91_SMC_NWEPULSE_(x) ((x) << 0) 94#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ 95#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) 96#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ 97#define AT91_SMC_NRDPULSE_(x) ((x) << 16) 98#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ 99#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) 100 101#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 102#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ 103#define AT91_SMC_NWECYCLE_(x) ((x) << 0) 104#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ 105#define AT91_SMC_NRDCYCLE_(x) ((x) << 16) 106 107#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 108#define AT91_SMC_READMODE (1 << 0) /* Read Mode */ 109#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ 110#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ 111#define AT91_SMC_EXNWMODE_DISABLE (0 << 4) 112#define AT91_SMC_EXNWMODE_FROZEN (2 << 4) 113#define AT91_SMC_EXNWMODE_READY (3 << 4) 114#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ 115#define AT91_SMC_BAT_SELECT (0 << 8) 116#define AT91_SMC_BAT_WRITE (1 << 8) 117#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ 118#define AT91_SMC_DBW_8 (0 << 12) 119#define AT91_SMC_DBW_16 (1 << 12) 120#define AT91_SMC_DBW_32 (2 << 12) 121#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ 122#define AT91_SMC_TDF_(x) ((x) << 16) 123#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ 124#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ 125#define AT91_SMC_PS (3 << 28) /* Page Size */ 126#define AT91_SMC_PS_4 (0 << 28) 127#define AT91_SMC_PS_8 (1 << 28) 128#define AT91_SMC_PS_16 (2 << 28) 129#define AT91_SMC_PS_32 (3 << 28) 130 131#if defined(AT91_SMC1) /* The AT91SAM9263 has 2 Static Memory contollers */ 132#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */ 133#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */ 134#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */ 135#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ 136#endif 137 138#endif 139#endif 140