1/* 2 * include/asm-arm/arch-ixp425/ixp425.h 3 * 4 * Register definitions for IXP425 5 * 6 * Copyright (C) 2002 Intel Corporation. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14#ifndef _ASM_ARM_IXP425_H_ 15#define _ASM_ARM_IXP425_H_ 16 17#define BIT(x) (1<<(x)) 18 19/* FIXME: Only this does work for u-boot... find out why... [RS] */ 20#define UBOOT_REG_FIX 1 21#ifdef UBOOT_REG_FIX 22# undef io_p2v 23# undef __REG 24# ifndef __ASSEMBLY__ 25# define io_p2v(PhAdd) (PhAdd) 26# define __REG(x) (*((volatile u32 *)io_p2v(x))) 27# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) 28# else 29# define __REG(x) (x) 30# endif 31#endif /* UBOOT_REG_FIX */ 32 33/* 34 * 35 * IXP425 Memory map: 36 * 37 * Phy Phy Size Map Size Virt Description 38 * ========================================================================= 39 * 40 * 0x00000000 0x10000000 SDRAM 1 41 * 42 * 0x10000000 0x10000000 SDRAM 2 43 * 44 * 0x20000000 0x10000000 SDRAM 3 45 * 46 * 0x30000000 0x10000000 SDRAM 4 47 * 48 * The above four are aliases to the same memory location (0x00000000) 49 * 50 * 0x48000000 0x4000000 PCI Memory 51 * 52 * 0x50000000 0x10000000 Not Mapped EXP BUS 53 * 54 * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr 55 * 56 * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG 57 * 58 * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG 59 * 60 * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL 61 * 62 * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG 63 */ 64 65/* 66 * SDRAM 67 */ 68#define IXP425_SDRAM_BASE (0x00000000) 69#define IXP425_SDRAM_BASE_ALT (0x10000000) 70 71 72/* 73 * PCI Configuration space 74 */ 75#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) 76#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) 77 78/* 79 * Expansion BUS Configuration registers 80 */ 81#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) 82#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) 83 84/* 85 * Peripheral space 86 */ 87#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) 88#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) 89 90/* 91 * SDRAM configuration registers 92 */ 93#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) 94 95/* 96 * Q Manager space .. not static mapped 97 */ 98#define IXP425_QMGR_BASE_PHYS (0x60000000) 99#define IXP425_QMGR_REGION_SIZE (0x00004000) 100 101/* 102 * Expansion BUS 103 * 104 * Expansion Bus 'lives' at either base1 or base 2 depending on the value of 105 * Exp Bus config registers: 106 * 107 * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, 108 * and The expansion bus to IXP425_EXP_BUS_BASE2 109 */ 110#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) 111#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) 112 113#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS 114 115#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) 116#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) 117 118#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) 119#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) 120#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) 121#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) 122#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) 123#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) 124#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) 125#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) 126 127#define IXP425_FLASH_WRITABLE (0x2) 128#define IXP425_FLASH_DEFAULT (0xbcd23c40) 129#define IXP425_FLASH_WRITE (0xbcd23c42) 130 131#define IXP425_EXP_CS0_OFFSET 0x00 132#define IXP425_EXP_CS1_OFFSET 0x04 133#define IXP425_EXP_CS2_OFFSET 0x08 134#define IXP425_EXP_CS3_OFFSET 0x0C 135#define IXP425_EXP_CS4_OFFSET 0x10 136#define IXP425_EXP_CS5_OFFSET 0x14 137#define IXP425_EXP_CS6_OFFSET 0x18 138#define IXP425_EXP_CS7_OFFSET 0x1C 139#define IXP425_EXP_CFG0_OFFSET 0x20 140#define IXP425_EXP_CFG1_OFFSET 0x24 141#define IXP425_EXP_CFG2_OFFSET 0x28 142#define IXP425_EXP_CFG3_OFFSET 0x2C 143 144/* 145 * Expansion Bus Controller registers. 146 */ 147#ifndef __ASSEMBLY__ 148#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) 149#else 150#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) 151#endif 152 153#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) 154#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) 155#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) 156#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) 157#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) 158#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) 159#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) 160#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) 161 162#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) 163#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) 164#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) 165#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) 166 167/* 168 * SDRAM Controller registers. 169 */ 170#define IXP425_SDR_CONFIG_OFFSET 0x00 171#define IXP425_SDR_REFRESH_OFFSET 0x04 172#define IXP425_SDR_IR_OFFSET 0x08 173 174#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) 175 176#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) 177#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) 178#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) 179 180/* 181 * UART registers 182 */ 183#define IXP425_UART1 0 184#define IXP425_UART2 0x1000 185 186#define IXP425_UART_RBR_OFFSET 0x00 187#define IXP425_UART_THR_OFFSET 0x00 188#define IXP425_UART_DLL_OFFSET 0x00 189#define IXP425_UART_IER_OFFSET 0x04 190#define IXP425_UART_DLH_OFFSET 0x04 191#define IXP425_UART_IIR_OFFSET 0x08 192#define IXP425_UART_FCR_OFFSET 0x00 193#define IXP425_UART_LCR_OFFSET 0x0c 194#define IXP425_UART_MCR_OFFSET 0x10 195#define IXP425_UART_LSR_OFFSET 0x14 196#define IXP425_UART_MSR_OFFSET 0x18 197#define IXP425_UART_SPR_OFFSET 0x1c 198#define IXP425_UART_ISR_OFFSET 0x20 199 200#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) 201 202#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) 203#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) 204#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) 205#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) 206#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) 207#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) 208#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) 209#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) 210#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) 211#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) 212#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) 213#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) 214#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) 215 216#define IER_DMAE (1 << 7) /* DMA Requests Enable */ 217#define IER_UUE (1 << 6) /* UART Unit Enable */ 218#define IER_NRZE (1 << 5) /* NRZ coding Enable */ 219#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ 220#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ 221#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ 222#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ 223#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ 224 225#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ 226#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ 227#define IIR_TOD (1 << 3) /* Time Out Detected */ 228#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ 229#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ 230#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ 231 232#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ 233#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ 234#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ 235#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ 236#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ 237#define FCR_ITL_1 (0) 238#define FCR_ITL_8 (FCR_ITL1) 239#define FCR_ITL_16 (FCR_ITL2) 240#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) 241 242#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ 243#define LCR_SB (1 << 6) /* Set Break */ 244#define LCR_STKYP (1 << 5) /* Sticky Parity */ 245#define LCR_EPS (1 << 4) /* Even Parity Select */ 246#define LCR_PEN (1 << 3) /* Parity Enable */ 247#define LCR_STB (1 << 2) /* Stop Bit */ 248#define LCR_WLS1 (1 << 1) /* Word Length Select */ 249#define LCR_WLS0 (1 << 0) /* Word Length Select */ 250 251#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ 252#define LSR_TEMT (1 << 6) /* Transmitter Empty */ 253#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ 254#define LSR_BI (1 << 4) /* Break Interrupt */ 255#define LSR_FE (1 << 3) /* Framing Error */ 256#define LSR_PE (1 << 2) /* Parity Error */ 257#define LSR_OE (1 << 1) /* Overrun Error */ 258#define LSR_DR (1 << 0) /* Data Ready */ 259 260#define MCR_LOOP (1 << 4) */ 261#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ 262#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ 263#define MCR_RTS (1 << 1) /* Request to Send */ 264#define MCR_DTR (1 << 0) /* Data Terminal Ready */ 265 266#define MSR_DCD (1 << 7) /* Data Carrier Detect */ 267#define MSR_RI (1 << 6) /* Ring Indicator */ 268#define MSR_DSR (1 << 5) /* Data Set Ready */ 269#define MSR_CTS (1 << 4) /* Clear To Send */ 270#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ 271#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ 272#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ 273#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ 274 275#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS 276/* 277 * Peripheral Space Registers 278 */ 279#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) 280#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) 281#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) 282#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) 283#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) 284#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) 285#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) 286#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) 287#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) 288#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) 289#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) 290#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) 291 292/* 293 * UART Register Definitions , Offsets only as there are 2 UARTS. 294 * IXP425_UART1_BASE , IXP425_UART2_BASE. 295 */ 296 297#undef UART_NO_RX_INTERRUPT 298 299#define IXP425_UART_XTAL 14745600 300 301/* 302 * Constants to make it easy to access Interrupt Controller registers 303 */ 304#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ 305#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ 306#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ 307#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ 308#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ 309#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ 310#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ 311#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ 312 313#define N_IRQS 32 314#define IXP425_TIMER_2_IRQ 11 315 316/* 317 * Interrupt Controller Register Definitions. 318 */ 319#ifndef __ASSEMBLY__ 320#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) 321#else 322#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) 323#endif 324 325#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) 326#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) 327#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) 328#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) 329#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) 330#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) 331#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) 332#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) 333 334/* 335 * Constants to make it easy to access GPIO registers 336 */ 337#define IXP425_GPIO_GPOUTR_OFFSET 0x00 338#define IXP425_GPIO_GPOER_OFFSET 0x04 339#define IXP425_GPIO_GPINR_OFFSET 0x08 340#define IXP425_GPIO_GPISR_OFFSET 0x0C 341#define IXP425_GPIO_GPIT1R_OFFSET 0x10 342#define IXP425_GPIO_GPIT2R_OFFSET 0x14 343#define IXP425_GPIO_GPCLKR_OFFSET 0x18 344#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C 345 346/* 347 * GPIO Register Definitions. 348 * [Only perform 32bit reads/writes] 349 */ 350#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) 351 352#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) 353#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) 354#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) 355#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) 356#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) 357#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) 358#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) 359#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) 360 361#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ 362 IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) 363 364/* 365 * Macros to make it easy to access the GPIO registers 366 */ 367#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) 368#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) 369#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) 370#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) 371#define GPIO_INT_ACT_LOW_SET(line) \ 372 *IXP425_GPIO_GPITR(line) = \ 373 (*IXP425_GPIO_GPITR(line) & \ 374 ~(0x7 << (((line) & 0x7) * 3))) | \ 375 (0x1 << (((line) & 0x7) * 3)) \ 376 377/* 378 * Constants to make it easy to access Timer Control/Status registers 379 */ 380#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ 381#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ 382#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ 383#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ 384#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ 385#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ 386#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ 387#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ 388#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ 389 390/* 391 * Operating System Timer Register Definitions. 392 */ 393 394#ifndef __ASSEMBLY__ 395#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) 396#else 397#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) 398#endif 399 400/* _B to avoid collision: also defined in npe/include/... */ 401#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) 402#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) 403#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) 404#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) 405#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) 406#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) 407#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) 408#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) 409#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) 410 411/* 412 * Timer register values and bit definitions 413 */ 414#define IXP425_OST_ENABLE BIT(0) 415#define IXP425_OST_ONE_SHOT BIT(1) 416/* Low order bits of reload value ignored */ 417#define IXP425_OST_RELOAD_MASK (0x3) 418#define IXP425_OST_DISABLED (0x0) 419#define IXP425_OSST_TIMER_1_PEND BIT(0) 420#define IXP425_OSST_TIMER_2_PEND BIT(1) 421#define IXP425_OSST_TIMER_TS_PEND BIT(2) 422#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) 423#define IXP425_OSST_TIMER_WARM_RESET BIT(4) 424 425/* 426 * Constants to make it easy to access PCI Control/Status registers 427 */ 428#define PCI_NP_AD_OFFSET 0x00 429#define PCI_NP_CBE_OFFSET 0x04 430#define PCI_NP_WDATA_OFFSET 0x08 431#define PCI_NP_RDATA_OFFSET 0x0c 432#define PCI_CRP_AD_CBE_OFFSET 0x10 433#define PCI_CRP_WDATA_OFFSET 0x14 434#define PCI_CRP_RDATA_OFFSET 0x18 435#define PCI_CSR_OFFSET 0x1c 436#define PCI_ISR_OFFSET 0x20 437#define PCI_INTEN_OFFSET 0x24 438#define PCI_DMACTRL_OFFSET 0x28 439#define PCI_AHBMEMBASE_OFFSET 0x2c 440#define PCI_AHBIOBASE_OFFSET 0x30 441#define PCI_PCIMEMBASE_OFFSET 0x34 442#define PCI_AHBDOORBELL_OFFSET 0x38 443#define PCI_PCIDOORBELL_OFFSET 0x3C 444#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 445#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 446#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 447#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C 448#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 449#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 450 451/* 452 * PCI Control/Status Registers 453 */ 454#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) 455 456#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) 457#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) 458#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) 459#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) 460#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) 461#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) 462#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) 463#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) 464#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) 465#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) 466#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) 467#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) 468#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) 469#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) 470#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) 471#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) 472#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) 473#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) 474#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) 475#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) 476#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) 477#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) 478 479/* 480 * PCI register values and bit definitions 481 */ 482 483/* CSR bit definitions */ 484#define PCI_CSR_HOST BIT(0) 485#define PCI_CSR_ARBEN BIT(1) 486#define PCI_CSR_ADS BIT(2) 487#define PCI_CSR_PDS BIT(3) 488#define PCI_CSR_ABE BIT(4) 489#define PCI_CSR_DBT BIT(5) 490#define PCI_CSR_ASE BIT(8) 491#define PCI_CSR_IC BIT(15) 492 493/* ISR (Interrupt status) Register bit definitions */ 494#define PCI_ISR_PSE BIT(0) 495#define PCI_ISR_PFE BIT(1) 496#define PCI_ISR_PPE BIT(2) 497#define PCI_ISR_AHBE BIT(3) 498#define PCI_ISR_APDC BIT(4) 499#define PCI_ISR_PADC BIT(5) 500#define PCI_ISR_ADB BIT(6) 501#define PCI_ISR_PDB BIT(7) 502 503/* INTEN (Interrupt Enable) Register bit definitions */ 504#define PCI_INTEN_PSE BIT(0) 505#define PCI_INTEN_PFE BIT(1) 506#define PCI_INTEN_PPE BIT(2) 507#define PCI_INTEN_AHBE BIT(3) 508#define PCI_INTEN_APDC BIT(4) 509#define PCI_INTEN_PADC BIT(5) 510#define PCI_INTEN_ADB BIT(6) 511#define PCI_INTEN_PDB BIT(7) 512 513/* 514 * Shift value for byte enable on NP cmd/byte enable register 515 */ 516#define IXP425_PCI_NP_CBE_BESL 4 517 518/* 519 * PCI commands supported by NP access unit 520 */ 521#define NP_CMD_IOREAD 0x2 522#define NP_CMD_IOWRITE 0x3 523#define NP_CMD_CONFIGREAD 0xa 524#define NP_CMD_CONFIGWRITE 0xb 525#define NP_CMD_MEMREAD 0x6 526#define NP_CMD_MEMWRITE 0x7 527 528#if 0 529#ifndef __ASSEMBLY__ 530extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); 531extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); 532extern void ixp425_pci_init(void *); 533#endif 534#endif 535 536/* 537 * Constants for CRP access into local config space 538 */ 539#define CRP_AD_CBE_BESL 20 540#define CRP_AD_CBE_WRITE BIT(16) 541 542/* 543 * Clock Speed Definitions. 544 */ 545#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ 546 547 548#endif 549