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23#ifndef __MACH_MX5_IOMUX_H__
24#define __MACH_MX5_IOMUX_H__
25
26#include <common.h>
27#include <asm/io.h>
28#include <asm/arch/imx-regs.h>
29#include <asm/arch/mx5x_pins.h>
30
31typedef unsigned int iomux_pin_name_t;
32
33
34typedef enum iomux_config {
35 IOMUX_CONFIG_ALT0,
36 IOMUX_CONFIG_ALT1,
37 IOMUX_CONFIG_ALT2,
38 IOMUX_CONFIG_ALT3,
39 IOMUX_CONFIG_ALT4,
40 IOMUX_CONFIG_ALT5,
41 IOMUX_CONFIG_ALT6,
42 IOMUX_CONFIG_ALT7,
43 IOMUX_CONFIG_GPIO,
44 IOMUX_CONFIG_SION = 0x1 << 4,
45} iomux_pin_cfg_t;
46
47
48typedef enum iomux_pad_config {
49 PAD_CTL_SRE_SLOW = 0x0 << 0,
50 PAD_CTL_SRE_FAST = 0x1 << 0,
51 PAD_CTL_DRV_LOW = 0x0 << 1,
52 PAD_CTL_DRV_MEDIUM = 0x1 << 1,
53 PAD_CTL_DRV_HIGH = 0x2 << 1,
54 PAD_CTL_DRV_MAX = 0x3 << 1,
55 PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3,
56 PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,
57 PAD_CTL_100K_PD = 0x0 << 4,
58 PAD_CTL_47K_PU = 0x1 << 4,
59 PAD_CTL_100K_PU = 0x2 << 4,
60 PAD_CTL_22K_PU = 0x3 << 4,
61 PAD_CTL_PUE_KEEPER = 0x0 << 6,
62 PAD_CTL_PUE_PULL = 0x1 << 6,
63 PAD_CTL_PKE_NONE = 0x0 << 7,
64 PAD_CTL_PKE_ENABLE = 0x1 << 7,
65 PAD_CTL_HYS_NONE = 0x0 << 8,
66 PAD_CTL_HYS_ENABLE = 0x1 << 8,
67 PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,
68 PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,
69 PAD_CTL_DRV_VOT_LOW = 0x0 << 13,
70 PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,
71} iomux_pad_config_t;
72
73
74typedef enum iomux_input_config {
75 INPUT_CTL_PATH0 = 0x0,
76 INPUT_CTL_PATH1,
77 INPUT_CTL_PATH2,
78 INPUT_CTL_PATH3,
79 INPUT_CTL_PATH4,
80 INPUT_CTL_PATH5,
81 INPUT_CTL_PATH6,
82 INPUT_CTL_PATH7,
83} iomux_input_config_t;
84
85void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
86void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config);
87void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config);
88unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin);
89void mxc_iomux_set_input(iomux_input_select_t input, u32 config);
90
91#endif
92