1/* 2 * (C) Copyright 2003 3 * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/************************************************ 25 * NAME : s3c24x0.h 26 * Version : 31.3.2003 27 * 28 * common stuff for SAMSUNG S3C24X0 SoC 29 ************************************************/ 30 31#ifndef __S3C24X0_H__ 32#define __S3C24X0_H__ 33 34/* Memory controller (see manual chapter 5) */ 35struct s3c24x0_memctl { 36 u32 bwscon; 37 u32 bankcon[8]; 38 u32 refresh; 39 u32 banksize; 40 u32 mrsrb6; 41 u32 mrsrb7; 42}; 43 44 45/* USB HOST (see manual chapter 12) */ 46struct s3c24x0_usb_host { 47 u32 HcRevision; 48 u32 HcControl; 49 u32 HcCommonStatus; 50 u32 HcInterruptStatus; 51 u32 HcInterruptEnable; 52 u32 HcInterruptDisable; 53 u32 HcHCCA; 54 u32 HcPeriodCuttendED; 55 u32 HcControlHeadED; 56 u32 HcControlCurrentED; 57 u32 HcBulkHeadED; 58 u32 HcBuldCurrentED; 59 u32 HcDoneHead; 60 u32 HcRmInterval; 61 u32 HcFmRemaining; 62 u32 HcFmNumber; 63 u32 HcPeriodicStart; 64 u32 HcLSThreshold; 65 u32 HcRhDescriptorA; 66 u32 HcRhDescriptorB; 67 u32 HcRhStatus; 68 u32 HcRhPortStatus1; 69 u32 HcRhPortStatus2; 70}; 71 72 73/* INTERRUPT (see manual chapter 14) */ 74struct s3c24x0_interrupt { 75 u32 srcpnd; 76 u32 intmod; 77 u32 intmsk; 78 u32 priority; 79 u32 intpnd; 80 u32 intoffset; 81#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) 82 u32 subsrcpnd; 83 u32 intsubmsk; 84#endif 85}; 86 87 88/* DMAS (see manual chapter 8) */ 89struct s3c24x0_dma { 90 u32 disrc; 91#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) 92 u32 disrcc; 93#endif 94 u32 didst; 95#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) 96 u32 didstc; 97#endif 98 u32 dcon; 99 u32 dstat; 100 u32 dcsrc; 101 u32 dcdst; 102 u32 dmasktrig; 103#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ 104 || defined(CONFIG_S3C2440) 105 u32 res[1]; 106#endif 107}; 108 109struct s3c24x0_dmas { 110 struct s3c24x0_dma dma[4]; 111}; 112 113 114/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ 115/* (see S3C2410 manual chapter 7) */ 116struct s3c24x0_clock_power { 117 u32 locktime; 118 u32 mpllcon; 119 u32 upllcon; 120 u32 clkcon; 121 u32 clkslow; 122 u32 clkdivn; 123#if defined(CONFIG_S3C2440) 124 u32 camdivn; 125#endif 126}; 127 128 129/* LCD CONTROLLER (see manual chapter 15) */ 130struct s3c24x0_lcd { 131 u32 lcdcon1; 132 u32 lcdcon2; 133 u32 lcdcon3; 134 u32 lcdcon4; 135 u32 lcdcon5; 136 u32 lcdsaddr1; 137 u32 lcdsaddr2; 138 u32 lcdsaddr3; 139 u32 redlut; 140 u32 greenlut; 141 u32 bluelut; 142 u32 res[8]; 143 u32 dithmode; 144 u32 tpal; 145#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) 146 u32 lcdintpnd; 147 u32 lcdsrcpnd; 148 u32 lcdintmsk; 149 u32 lpcsel; 150#endif 151}; 152 153 154#ifdef CONFIG_S3C2410 155/* NAND FLASH (see S3C2410 manual chapter 6) */ 156struct s3c2410_nand { 157 u32 nfconf; 158 u32 nfcmd; 159 u32 nfaddr; 160 u32 nfdata; 161 u32 nfstat; 162 u32 nfecc; 163}; 164#endif 165#ifdef CONFIG_S3C2440 166/* NAND FLASH (see S3C2440 manual chapter 6) */ 167struct s3c2440_nand { 168 u32 nfconf; 169 u32 nfcont; 170 u32 nfcmd; 171 u32 nfaddr; 172 u32 nfdata; 173 u32 nfeccd0; 174 u32 nfeccd1; 175 u32 nfeccd; 176 u32 nfstat; 177 u32 nfstat0; 178 u32 nfstat1; 179}; 180#endif 181 182 183/* UART (see manual chapter 11) */ 184struct s3c24x0_uart { 185 u32 ulcon; 186 u32 ucon; 187 u32 ufcon; 188 u32 umcon; 189 u32 utrstat; 190 u32 uerstat; 191 u32 ufstat; 192 u32 umstat; 193#ifdef __BIG_ENDIAN 194 u8 res1[3]; 195 u8 utxh; 196 u8 res2[3]; 197 u8 urxh; 198#else /* Little Endian */ 199 u8 utxh; 200 u8 res1[3]; 201 u8 urxh; 202 u8 res2[3]; 203#endif 204 u32 ubrdiv; 205}; 206 207 208/* PWM TIMER (see manual chapter 10) */ 209struct s3c24x0_timer { 210 u32 tcntb; 211 u32 tcmpb; 212 u32 tcnto; 213}; 214 215struct s3c24x0_timers { 216 u32 tcfg0; 217 u32 tcfg1; 218 u32 tcon; 219 struct s3c24x0_timer ch[4]; 220 u32 tcntb4; 221 u32 tcnto4; 222}; 223 224 225/* USB DEVICE (see manual chapter 13) */ 226struct s3c24x0_usb_dev_fifos { 227#ifdef __BIG_ENDIAN 228 u8 res[3]; 229 u8 ep_fifo_reg; 230#else /* little endian */ 231 u8 ep_fifo_reg; 232 u8 res[3]; 233#endif 234}; 235 236struct s3c24x0_usb_dev_dmas { 237#ifdef __BIG_ENDIAN 238 u8 res1[3]; 239 u8 ep_dma_con; 240 u8 res2[3]; 241 u8 ep_dma_unit; 242 u8 res3[3]; 243 u8 ep_dma_fifo; 244 u8 res4[3]; 245 u8 ep_dma_ttc_l; 246 u8 res5[3]; 247 u8 ep_dma_ttc_m; 248 u8 res6[3]; 249 u8 ep_dma_ttc_h; 250#else /* little endian */ 251 u8 ep_dma_con; 252 u8 res1[3]; 253 u8 ep_dma_unit; 254 u8 res2[3]; 255 u8 ep_dma_fifo; 256 u8 res3[3]; 257 u8 ep_dma_ttc_l; 258 u8 res4[3]; 259 u8 ep_dma_ttc_m; 260 u8 res5[3]; 261 u8 ep_dma_ttc_h; 262 u8 res6[3]; 263#endif 264}; 265 266struct s3c24x0_usb_device { 267#ifdef __BIG_ENDIAN 268 u8 res1[3]; 269 u8 func_addr_reg; 270 u8 res2[3]; 271 u8 pwr_reg; 272 u8 res3[3]; 273 u8 ep_int_reg; 274 u8 res4[15]; 275 u8 usb_int_reg; 276 u8 res5[3]; 277 u8 ep_int_en_reg; 278 u8 res6[15]; 279 u8 usb_int_en_reg; 280 u8 res7[3]; 281 u8 frame_num1_reg; 282 u8 res8[3]; 283 u8 frame_num2_reg; 284 u8 res9[3]; 285 u8 index_reg; 286 u8 res10[7]; 287 u8 maxp_reg; 288 u8 res11[3]; 289 u8 ep0_csr_in_csr1_reg; 290 u8 res12[3]; 291 u8 in_csr2_reg; 292 u8 res13[7]; 293 u8 out_csr1_reg; 294 u8 res14[3]; 295 u8 out_csr2_reg; 296 u8 res15[3]; 297 u8 out_fifo_cnt1_reg; 298 u8 res16[3]; 299 u8 out_fifo_cnt2_reg; 300#else /* little endian */ 301 u8 func_addr_reg; 302 u8 res1[3]; 303 u8 pwr_reg; 304 u8 res2[3]; 305 u8 ep_int_reg; 306 u8 res3[15]; 307 u8 usb_int_reg; 308 u8 res4[3]; 309 u8 ep_int_en_reg; 310 u8 res5[15]; 311 u8 usb_int_en_reg; 312 u8 res6[3]; 313 u8 frame_num1_reg; 314 u8 res7[3]; 315 u8 frame_num2_reg; 316 u8 res8[3]; 317 u8 index_reg; 318 u8 res9[7]; 319 u8 maxp_reg; 320 u8 res10[7]; 321 u8 ep0_csr_in_csr1_reg; 322 u8 res11[3]; 323 u8 in_csr2_reg; 324 u8 res12[3]; 325 u8 out_csr1_reg; 326 u8 res13[7]; 327 u8 out_csr2_reg; 328 u8 res14[3]; 329 u8 out_fifo_cnt1_reg; 330 u8 res15[3]; 331 u8 out_fifo_cnt2_reg; 332 u8 res16[3]; 333#endif /* __BIG_ENDIAN */ 334 struct s3c24x0_usb_dev_fifos fifo[5]; 335 struct s3c24x0_usb_dev_dmas dma[5]; 336}; 337 338 339/* WATCH DOG TIMER (see manual chapter 18) */ 340struct s3c24x0_watchdog { 341 u32 wtcon; 342 u32 wtdat; 343 u32 wtcnt; 344}; 345 346 347/* IIC (see manual chapter 20) */ 348struct s3c24x0_i2c { 349 u32 iiccon; 350 u32 iicstat; 351 u32 iicadd; 352 u32 iicds; 353}; 354 355 356/* IIS (see manual chapter 21) */ 357struct s3c24x0_i2s { 358#ifdef __BIG_ENDIAN 359 u16 res1; 360 u16 iiscon; 361 u16 res2; 362 u16 iismod; 363 u16 res3; 364 u16 iispsr; 365 u16 res4; 366 u16 iisfcon; 367 u16 res5; 368 u16 iisfifo; 369#else /* little endian */ 370 u16 iiscon; 371 u16 res1; 372 u16 iismod; 373 u16 res2; 374 u16 iispsr; 375 u16 res3; 376 u16 iisfcon; 377 u16 res4; 378 u16 iisfifo; 379 u16 res5; 380#endif 381}; 382 383 384/* I/O PORT (see manual chapter 9) */ 385struct s3c24x0_gpio { 386#ifdef CONFIG_S3C2400 387 u32 pacon; 388 u32 padat; 389 390 u32 pbcon; 391 u32 pbdat; 392 u32 pbup; 393 394 u32 pccon; 395 u32 pcdat; 396 u32 pcup; 397 398 u32 pdcon; 399 u32 pddat; 400 u32 pdup; 401 402 u32 pecon; 403 u32 pedat; 404 u32 peup; 405 406 u32 pfcon; 407 u32 pfdat; 408 u32 pfup; 409 410 u32 pgcon; 411 u32 pgdat; 412 u32 pgup; 413 414 u32 opencr; 415 416 u32 misccr; 417 u32 extint; 418#endif 419#ifdef CONFIG_S3C2410 420 u32 gpacon; 421 u32 gpadat; 422 u32 res1[2]; 423 u32 gpbcon; 424 u32 gpbdat; 425 u32 gpbup; 426 u32 res2; 427 u32 gpccon; 428 u32 gpcdat; 429 u32 gpcup; 430 u32 res3; 431 u32 gpdcon; 432 u32 gpddat; 433 u32 gpdup; 434 u32 res4; 435 u32 gpecon; 436 u32 gpedat; 437 u32 gpeup; 438 u32 res5; 439 u32 gpfcon; 440 u32 gpfdat; 441 u32 gpfup; 442 u32 res6; 443 u32 gpgcon; 444 u32 gpgdat; 445 u32 gpgup; 446 u32 res7; 447 u32 gphcon; 448 u32 gphdat; 449 u32 gphup; 450 u32 res8; 451 452 u32 misccr; 453 u32 dclkcon; 454 u32 extint0; 455 u32 extint1; 456 u32 extint2; 457 u32 eintflt0; 458 u32 eintflt1; 459 u32 eintflt2; 460 u32 eintflt3; 461 u32 eintmask; 462 u32 eintpend; 463 u32 gstatus0; 464 u32 gstatus1; 465 u32 gstatus2; 466 u32 gstatus3; 467 u32 gstatus4; 468#endif 469#if defined(CONFIG_S3C2440) 470 u32 gpacon; 471 u32 gpadat; 472 u32 res1[2]; 473 u32 gpbcon; 474 u32 gpbdat; 475 u32 gpbup; 476 u32 res2; 477 u32 gpccon; 478 u32 gpcdat; 479 u32 gpcup; 480 u32 res3; 481 u32 gpdcon; 482 u32 gpddat; 483 u32 gpdup; 484 u32 res4; 485 u32 gpecon; 486 u32 gpedat; 487 u32 gpeup; 488 u32 res5; 489 u32 gpfcon; 490 u32 gpfdat; 491 u32 gpfup; 492 u32 res6; 493 u32 gpgcon; 494 u32 gpgdat; 495 u32 gpgup; 496 u32 res7; 497 u32 gphcon; 498 u32 gphdat; 499 u32 gphup; 500 u32 res8; 501 502 u32 misccr; 503 u32 dclkcon; 504 u32 extint0; 505 u32 extint1; 506 u32 extint2; 507 u32 eintflt0; 508 u32 eintflt1; 509 u32 eintflt2; 510 u32 eintflt3; 511 u32 eintmask; 512 u32 eintpend; 513 u32 gstatus0; 514 u32 gstatus1; 515 u32 gstatus2; 516 u32 gstatus3; 517 u32 gstatus4; 518 519 u32 res9; 520 u32 dsc0; 521 u32 dsc1; 522 u32 mslcon; 523 u32 gpjcon; 524 u32 gpjdat; 525 u32 gpjup; 526 u32 res10; 527#endif 528}; 529 530 531/* RTC (see manual chapter 17) */ 532struct s3c24x0_rtc { 533#ifdef __BIG_ENDIAN 534 u8 res1[67]; 535 u8 rtccon; 536 u8 res2[3]; 537 u8 ticnt; 538 u8 res3[11]; 539 u8 rtcalm; 540 u8 res4[3]; 541 u8 almsec; 542 u8 res5[3]; 543 u8 almmin; 544 u8 res6[3]; 545 u8 almhour; 546 u8 res7[3]; 547 u8 almdate; 548 u8 res8[3]; 549 u8 almmon; 550 u8 res9[3]; 551 u8 almyear; 552 u8 res10[3]; 553 u8 rtcrst; 554 u8 res11[3]; 555 u8 bcdsec; 556 u8 res12[3]; 557 u8 bcdmin; 558 u8 res13[3]; 559 u8 bcdhour; 560 u8 res14[3]; 561 u8 bcddate; 562 u8 res15[3]; 563 u8 bcdday; 564 u8 res16[3]; 565 u8 bcdmon; 566 u8 res17[3]; 567 u8 bcdyear; 568#else /* little endian */ 569 u8 res0[64]; 570 u8 rtccon; 571 u8 res1[3]; 572 u8 ticnt; 573 u8 res2[11]; 574 u8 rtcalm; 575 u8 res3[3]; 576 u8 almsec; 577 u8 res4[3]; 578 u8 almmin; 579 u8 res5[3]; 580 u8 almhour; 581 u8 res6[3]; 582 u8 almdate; 583 u8 res7[3]; 584 u8 almmon; 585 u8 res8[3]; 586 u8 almyear; 587 u8 res9[3]; 588 u8 rtcrst; 589 u8 res10[3]; 590 u8 bcdsec; 591 u8 res11[3]; 592 u8 bcdmin; 593 u8 res12[3]; 594 u8 bcdhour; 595 u8 res13[3]; 596 u8 bcddate; 597 u8 res14[3]; 598 u8 bcdday; 599 u8 res15[3]; 600 u8 bcdmon; 601 u8 res16[3]; 602 u8 bcdyear; 603 u8 res17[3]; 604#endif 605}; 606 607 608/* ADC (see manual chapter 16) */ 609struct s3c2400_adc { 610 u32 adccon; 611 u32 adcdat; 612}; 613 614 615/* ADC (see manual chapter 16) */ 616struct s3c2410_adc { 617 u32 adccon; 618 u32 adctsc; 619 u32 adcdly; 620 u32 adcdat0; 621 u32 adcdat1; 622}; 623 624 625/* SPI (see manual chapter 22) */ 626struct s3c24x0_spi_channel { 627 u8 spcon; 628 u8 res1[3]; 629 u8 spsta; 630 u8 res2[3]; 631 u8 sppin; 632 u8 res3[3]; 633 u8 sppre; 634 u8 res4[3]; 635 u8 sptdat; 636 u8 res5[3]; 637 u8 sprdat; 638 u8 res6[3]; 639 u8 res7[16]; 640}; 641 642struct s3c24x0_spi { 643 struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; 644}; 645 646 647/* MMC INTERFACE (see S3C2400 manual chapter 19) */ 648struct s3c2400_mmc { 649#ifdef __BIG_ENDIAN 650 u8 res1[3]; 651 u8 mmcon; 652 u8 res2[3]; 653 u8 mmcrr; 654 u8 res3[3]; 655 u8 mmfcon; 656 u8 res4[3]; 657 u8 mmsta; 658 u16 res5; 659 u16 mmfsta; 660 u8 res6[3]; 661 u8 mmpre; 662 u16 res7; 663 u16 mmlen; 664 u8 res8[3]; 665 u8 mmcr7; 666 u32 mmrsp[4]; 667 u8 res9[3]; 668 u8 mmcmd0; 669 u32 mmcmd1; 670 u16 res10; 671 u16 mmcr16; 672 u8 res11[3]; 673 u8 mmdat; 674#else 675 u8 mmcon; 676 u8 res1[3]; 677 u8 mmcrr; 678 u8 res2[3]; 679 u8 mmfcon; 680 u8 res3[3]; 681 u8 mmsta; 682 u8 res4[3]; 683 u16 mmfsta; 684 u16 res5; 685 u8 mmpre; 686 u8 res6[3]; 687 u16 mmlen; 688 u16 res7; 689 u8 mmcr7; 690 u8 res8[3]; 691 u32 mmrsp[4]; 692 u8 mmcmd0; 693 u8 res9[3]; 694 u32 mmcmd1; 695 u16 mmcr16; 696 u16 res10; 697 u8 mmdat; 698 u8 res11[3]; 699#endif 700}; 701 702 703/* SD INTERFACE (see S3C2410 manual chapter 19) */ 704struct s3c2410_sdi { 705 u32 sdicon; 706 u32 sdipre; 707 u32 sdicarg; 708 u32 sdiccon; 709 u32 sdicsta; 710 u32 sdirsp0; 711 u32 sdirsp1; 712 u32 sdirsp2; 713 u32 sdirsp3; 714 u32 sdidtimer; 715 u32 sdibsize; 716 u32 sdidcon; 717 u32 sdidcnt; 718 u32 sdidsta; 719 u32 sdifsta; 720#ifdef __BIG_ENDIAN 721 u8 res[3]; 722 u8 sdidat; 723#else 724 u8 sdidat; 725 u8 res[3]; 726#endif 727 u32 sdiimsk; 728}; 729 730#endif /*__S3C24X0_H__*/ 731