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34#include <common.h>
35#include <mpc86xx.h>
36#include <command.h>
37#include <asm/processor.h>
38#ifdef CONFIG_POST
39#include <post.h>
40#endif
41
42int interrupt_init_cpu(unsigned long *decrementer_count)
43{
44 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
45 volatile ccsr_pic_t *pic = &immr->im_pic;
46
47#ifdef CONFIG_POST
48
49
50
51
52
53 ulong post_word = post_word_load();
54#endif
55
56 pic->gcr = MPC86xx_PICGCR_RST;
57 while (pic->gcr & MPC86xx_PICGCR_RST)
58 ;
59 pic->gcr = MPC86xx_PICGCR_MODE;
60
61 *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
62 debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
63 (get_tbclk() / 1000000),
64 *decrementer_count);
65
66#ifdef CONFIG_INTERRUPTS
67
68 pic->iivpr1 = 0x810001;
69 debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
70
71 pic->iivpr2 = 0x810002;
72 debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
73
74 pic->iivpr3 = 0x810003;
75 debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
76
77#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
78 pic->iivpr8 = 0x810008;
79 debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
80#endif
81#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
82 pic->iivpr9 = 0x810009;
83 debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
84#endif
85
86 pic->ctpr = 0;
87#endif
88
89#ifdef CONFIG_POST
90 post_word_store(post_word);
91#endif
92
93 return 0;
94}
95
96
97
98
99
100
101void timer_interrupt_cpu(struct pt_regs *regs)
102{
103
104}
105
106
107
108
109void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
110{
111}
112
113void irq_free_handler(int vec)
114{
115}
116
117
118
119
120int do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
121{
122 return 0;
123}
124
125
126
127
128void external_interrupt(struct pt_regs *regs)
129{
130 puts("external_interrupt (oops!)\n");
131}
132