LXR uboot/arch/powerpc/include/asm/fsl

   1/*
   2 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License as
   6 * published by the Free Software Foundation; either version 2 of
   7 * the License, or (at your option) any later version.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU General Public License
  15 * along with this program; if not, write to the Free Software
  16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17 * MA 02111-1307 USA
  18 *
  19 */
  20
  21#ifndef __FSL_PCI_H_
  22#define __FSL_PCI_H_
  23
  24#include <asm/fsl_law.h>
  25#include <asm/fsl_serdes.h>
  26#include <pci.h>
  27
  28#define PEX_IP_BLK_REV_2_2      0x02080202
  29#define PEX_IP_BLK_REV_2_3      0x02080203
  30
  31int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
  32int fsl_is_pci_agent(struct pci_controller *hose);
  33void fsl_pci_config_unlock(struct pci_controller *hose);
  34void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
  35
  36/*
  37 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
  38 */
  39
  40/*
  41 * PCI Translation Registers
  42 */
  43typedef struct pci_outbound_window {
  44        u32     potar;          /* 0x00 - Address */
  45        u32     potear;         /* 0x04 - Address Extended */
  46        u32     powbar;         /* 0x08 - Window Base Address */
  47        u32     res1;
  48        u32     powar;          /* 0x10 - Window Attributes */
  49#define POWAR_EN        0x80000000
  50#define POWAR_IO_READ   0x00080000
  51#define POWAR_MEM_READ  0x00040000
  52#define POWAR_IO_WRITE  0x00008000
  53#define POWAR_MEM_WRITE 0x00004000
  54        u32     res2[3];
  55} pot_t;
  56
  57typedef struct pci_inbound_window {
  58        u32     pitar;          /* 0x00 - Address */
  59        u32     res1;
  60        u32     piwbar;         /* 0x08 - Window Base Address */
  61        u32     piwbear;        /* 0x0c - Window Base Address Extended */
  62        u32     piwar;          /* 0x10 - Window Attributes */
  63#define PIWAR_EN                0x80000000
  64#define PIWAR_PF                0x20000000
  65#define PIWAR_LOCAL             0x00f00000
  66#define PIWAR_READ_SNOOP        0x00050000
  67#define PIWAR_WRITE_SNOOP       0x00005000
  68        u32     res2[3];
  69} pit_t;
  70
  71/* PCI/PCI Express Registers */
  72typedef struct ccsr_pci {
  73        u32     cfg_addr;       /* 0x000 - PCI Configuration Address Register */
  74        u32     cfg_data;       /* 0x004 - PCI Configuration Data Register */
  75        u32     int_ack;        /* 0x008 - PCI Interrupt Acknowledge Register */
  76        u32     out_comp_to;    /* 0x00C - PCI Outbound Completion Timeout Register */
  77        u32     out_conf_to;    /* 0x010 - PCI Configuration Timeout Register */
  78        u32     config;         /* 0x014 - PCIE CONFIG Register */
  79        u32     int_status;     /* 0x018 - PCIE interrupt status register */
  80        char    res2[4];
  81        u32     pme_msg_det;    /* 0x020 - PCIE PME & message detect register */
  82        u32     pme_msg_dis;    /* 0x024 - PCIE PME & message disable register */
  83        u32     pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
  84        u32     pm_command;     /* 0x02c - PCIE PM Command register */
  85        char    res4[3016];     /*     (- #xbf8  #x30)3016 */
  86        u32     block_rev1;     /* 0xbf8 - PCIE Block Revision register 1 */
  87        u32     block_rev2;     /* 0xbfc - PCIE Block Revision register 2 */
  88
  89        pot_t   pot[5];         /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
  90        u32     res5[24];
  91        pit_t   pmit;           /* 0xd00 - 0xd9c Inbound ATMU's MSI */
  92        u32     res6[24];
  93        pit_t   pit[4];         /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
  94
  95#define PIT3 0
  96#define PIT2 1
  97#define PIT1 2
  98
  99#if 0
 100        u32     potar0;         /* 0xc00 - PCI Outbound Transaction Address Register 0 */
 101        u32     potear0;        /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
 102        char    res5[8];
 103        u32     powar0;         /* 0xc10 - PCI Outbound Window Attributes Register 0 */
 104        char    res6[12];
 105        u32     potar1;         /* 0xc20 - PCI Outbound Transaction Address Register 1 */
 106        u32     potear1;        /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
 107        u32     powbar1;        /* 0xc28 - PCI Outbound Window Base Address Register 1 */
 108        char    res7[4];
 109        u32     powar1;         /* 0xc30 - PCI Outbound Window Attributes Register 1 */
 110        char    res8[12];
 111        u32     potar2;         /* 0xc40 - PCI Outbound Transaction Address Register 2 */
 112        u32     potear2;        /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
 113        u32     powbar2;        /* 0xc48 - PCI Outbound Window Base Address Register 2 */
 114        char    res9[4];
 115        u32     powar2;         /* 0xc50 - PCI Outbound Window Attributes Register 2 */
 116        char    res10[12];
 117        u32     potar3;         /* 0xc60 - PCI Outbound Transaction Address Register 3 */
 118        u32     potear3;        /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
 119        u32     powbar3;        /* 0xc68 - PCI Outbound Window Base Address Register 3 */
 120        char    res11[4];
 121        u32     powar3;         /* 0xc70 - PCI Outbound Window Attributes Register 3 */
 122        char    res12[12];
 123        u32     potar4;         /* 0xc80 - PCI Outbound Transaction Address Register 4 */
 124        u32     potear4;        /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
 125        u32     powbar4;        /* 0xc88 - PCI Outbound Window Base Address Register 4 */
 126        char    res13[4];
 127        u32     powar4;         /* 0xc90 - PCI Outbound Window Attributes Register 4 */
 128        char    res14[268];
 129        u32     pitar3;         /* 0xda0 - PCI Inbound Translation Address Register 3 */
 130        char    res15[4];
 131        u32     piwbar3;        /* 0xda8 - PCI Inbound Window Base Address Register 3 */
 132        u32     piwbear3;       /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
 133        u32     piwar3;         /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
 134        char    res16[12];
 135        u32     pitar2;         /* 0xdc0 - PCI Inbound Translation Address Register 2 */
 136        char    res17[4];
 137        u32     piwbar2;        /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
 138        u32     piwbear2;       /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
 139        u32     piwar2;         /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
 140        char    res18[12];
 141        u32     pitar1;         /* 0xde0 - PCI Inbound Translation Address Register 1 */
 142        char    res19[4];
 143        u32     piwbar1;        /* 0xde8 - PCI Inbound Window Base Address Register 1 */
 144        char    res20[4];
 145        u32     piwar1;         /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
 146        char    res21[12];
 147#endif
 148        u32     pedr;           /* 0xe00 - PCI Error Detect Register */
 149        u32     pecdr;          /* 0xe04 - PCI Error Capture Disable Register */
 150        u32     peer;           /* 0xe08 - PCI Error Interrupt Enable Register */
 151        u32     peattrcr;       /* 0xe0c - PCI Error Attributes Capture Register */
 152        u32     peaddrcr;       /* 0xe10 - PCI Error Address Capture Register */
 153/*      u32     perr_disr        * 0xe10 - PCIE Erorr Disable Register */
 154        u32     peextaddrcr;    /* 0xe14 - PCI  Error Extended Address Capture Register */
 155        u32     pedlcr;         /* 0xe18 - PCI Error Data Low Capture Register */
 156        u32     pedhcr;         /* 0xe1c - PCI Error Error Data High Capture Register */
 157        u32     gas_timr;       /* 0xe20 - PCI Gasket Timer Register */
 158/*      u32     perr_cap_stat;   * 0xe20 - PCIE Error Capture Status Register */
 159        char    res22[4];
 160        u32     perr_cap0;      /* 0xe28 - PCIE Error Capture Register 0 */
 161        u32     perr_cap1;      /* 0xe2c - PCIE Error Capture Register 1 */
 162        u32     perr_cap2;      /* 0xe30 - PCIE Error Capture Register 2 */
 163        u32     perr_cap3;      /* 0xe34 - PCIE Error Capture Register 3 */
 164        char    res23[200];
 165        u32     pdb_stat;       /* 0xf00 - PCIE Debug Status */
 166        char    res24[252];
 167} ccsr_fsl_pci_t;
 168#define PCIE_CONFIG_PC  0x00020000
 169#define PCIE_CONFIG_OB_CK       0x00002000
 170#define PCIE_CONFIG_SAC 0x00000010
 171#define PCIE_CONFIG_SP  0x80000002
 172#define PCIE_CONFIG_SCC 0x80000001
 173
 174struct fsl_pci_info {
 175        unsigned long regs;
 176        pci_addr_t mem_bus;
 177        phys_size_t mem_phys;
 178        pci_size_t mem_size;
 179        pci_addr_t io_bus;
 180        phys_size_t io_phys;
 181        pci_size_t io_size;
 182        enum law_trgt_if law;
 183        int pci_num;
 184};
 185
 186void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
 187int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 188                                struct pci_controller *hose, int busno);
 189int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
 190                        struct fsl_pci_info *pci_info);
 191int fsl_pcie_init_board(int busno);
 192
 193#define SET_STD_PCI_INFO(x, num) \
 194{                       \
 195        x.regs = CONFIG_SYS_PCI##num##_ADDR;    \
 196        x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
 197        x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
 198        x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
 199        x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
 200        x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
 201        x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
 202        x.law = LAW_TRGT_IF_PCI_##num; \
 203        x.pci_num = num; \
 204}
 205
 206#define SET_STD_PCIE_INFO(x, num) \
 207{                       \
 208        x.regs = CONFIG_SYS_PCIE##num##_ADDR;   \
 209        x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
 210        x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
 211        x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
 212        x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
 213        x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
 214        x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
 215        x.law = LAW_TRGT_IF_PCIE_##num; \
 216        x.pci_num = num; \
 217}
 218
 219#define __FT_FSL_PCI_SETUP(blob, compat, num) \
 220        ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
 221
 222#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
 223        ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
 224
 225#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
 226#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
 227
 228#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
 229#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
 230#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
 231#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
 232
 233#if !defined(CONFIG_PCI)
 234#define FT_FSL_PCI_SETUP
 235#elif defined(CONFIG_FSL_CORENET)
 236#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
 237#define FT_FSL_PCI_SETUP \
 238        FT_FSL_PCIE1_SETUP; \
 239        FT_FSL_PCIE2_SETUP; \
 240        FT_FSL_PCIE3_SETUP; \
 241        FT_FSL_PCIE4_SETUP;
 242#define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
 243#elif defined(CONFIG_MPC85xx)
 244#define FSL_PCI_COMPAT  "fsl,mpc8540-pci"
 245#ifdef CONFIG_SYS_FSL_PCIE_COMPAT
 246#define FSL_PCIE_COMPAT CONFIG_SYS_FSL_PCIE_COMPAT
 247#else
 248#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
 249#endif
 250#define FT_FSL_PCI_SETUP \
 251        FT_FSL_PCI1_SETUP; \
 252        FT_FSL_PCI2_SETUP; \
 253        FT_FSL_PCIE1_SETUP; \
 254        FT_FSL_PCIE2_SETUP; \
 255        FT_FSL_PCIE3_SETUP;
 256#define FT_FSL_PCIE_SETUP \
 257        FT_FSL_PCIE1_SETUP; \
 258        FT_FSL_PCIE2_SETUP; \
 259        FT_FSL_PCIE3_SETUP;
 260#elif defined(CONFIG_MPC86xx)
 261#define FSL_PCI_COMPAT  "fsl,mpc8610-pci"
 262#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
 263#define FT_FSL_PCI_SETUP \
 264        FT_FSL_PCI1_SETUP; \
 265        FT_FSL_PCIE1_SETUP; \
 266        FT_FSL_PCIE2_SETUP;
 267#else
 268#error FT_FSL_PCI_SETUP not defined
 269#endif
 270
 271
 272#endif
 273