LXR uboot/arch/sparc/include/asm/processor.h

   1/* SPARC Processor specifics
   2 * taken from the SPARC port of Linux (ptrace.h).
   3 *
   4 * (C) Copyright 2007
   5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 *
  22 */
  23
  24#ifndef __ASM_SPARC_PROCESSOR_H
  25#define __ASM_SPARC_PROCESSOR_H
  26
  27#include <asm/arch/asi.h>
  28
  29#ifdef CONFIG_LEON
  30
  31/* All LEON processors supported */
  32#include <asm/leon.h>
  33
  34#else
  35/* other processors */
  36#error Unknown SPARC Processor
  37#endif
  38
  39#ifndef __ASSEMBLY__
  40
  41/* flush data cache */
  42static __inline__ void sparc_dcache_flush_all(void)
  43{
  44      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH):"memory");
  45}
  46
  47/* flush instruction cache */
  48static __inline__ void sparc_icache_flush_all(void)
  49{
  50      __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH):"memory");
  51}
  52
  53/* do a cache miss load */
  54static __inline__ unsigned long long sparc_load_reg_cachemiss_qword(unsigned
  55                                                                    long paddr)
  56{
  57        unsigned long long retval;
  58        __asm__ __volatile__("ldda [%1] %2, %0\n\t":
  59                             "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  60        return retval;
  61}
  62
  63static __inline__ unsigned long sparc_load_reg_cachemiss(unsigned long paddr)
  64{
  65        unsigned long retval;
  66        __asm__ __volatile__("lda [%1] %2, %0\n\t":
  67                             "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  68        return retval;
  69}
  70
  71static __inline__ unsigned short sparc_load_reg_cachemiss_word(unsigned long
  72                                                               paddr)
  73{
  74        unsigned short retval;
  75        __asm__ __volatile__("lduha [%1] %2, %0\n\t":
  76                             "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  77        return retval;
  78}
  79
  80static __inline__ unsigned char sparc_load_reg_cachemiss_byte(unsigned long
  81                                                              paddr)
  82{
  83        unsigned char retval;
  84        __asm__ __volatile__("lduba [%1] %2, %0\n\t":
  85                             "=r"(retval):"r"(paddr), "i"(ASI_CACHEMISS));
  86        return retval;
  87}
  88
  89/* do a physical address bypass write, i.e. for 0x80000000 */
  90static __inline__ void sparc_store_reg_bypass(unsigned long paddr,
  91                                              unsigned long value)
  92{
  93        __asm__ __volatile__("sta %0, [%1] %2\n\t"::"r"(value), "r"(paddr),
  94                             "i"(ASI_BYPASS):"memory");
  95}
  96
  97static __inline__ unsigned long sparc_load_reg_bypass(unsigned long paddr)
  98{
  99        unsigned long retval;
 100        __asm__ __volatile__("lda [%1] %2, %0\n\t":
 101                             "=r"(retval):"r"(paddr), "i"(ASI_BYPASS));
 102        return retval;
 103}
 104
 105/* Macros for bypassing cache when reading */
 106#define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
 107#define SPARC_NOCACHE_READ(address)       sparc_load_reg_cachemiss((unsigned int)(address))
 108#define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
 109#define SPARC_NOCACHE_READ_BYTE(address)  sparc_load_reg_cachemiss_byte((unsigned int)(address))
 110
 111#define SPARC_BYPASS_READ(address)        sparc_load_reg_bypass((unsigned int)(address))
 112#define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
 113
 114#endif
 115
 116#endif                          /* __ASM_SPARC_PROCESSOR_H */
 117