LXR uboot/board/fads/fads.c

   1/*
   2 * (C) Copyright 2000-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#include <config.h>
  27#include <common.h>
  28#include <mpc8xx.h>
  29#include <pcmcia.h>
  30
  31#define _NOT_USED_      0xFFFFFFFF
  32
  33/* ========================================================================= */
  34
  35#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
  36
  37#if defined(CONFIG_DRAM_50MHZ)
  38/* 50MHz tables */
  39static const uint dram_60ns[] =
  40{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
  41  0x00ffec00, 0x37ffec47, _NOT_USED_, _NOT_USED_,
  42  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
  43  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
  44  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
  45  0x3fffc847, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  46  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
  47  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  48  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
  49  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  50  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
  51  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  52  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
  53  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
  54  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
  56
  57static const uint dram_70ns[] =
  58{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
  59  0x00ffcc00, 0x37ffcc47, _NOT_USED_, _NOT_USED_,
  60  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
  61  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
  62  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
  63  0x00ffec00, 0x3fffec47, _NOT_USED_, _NOT_USED_,
  64  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
  65  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  66  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
  67  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  68  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
  69  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  70  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
  71  0x7fffcc06, 0xffffcc85, 0xffffcc05, _NOT_USED_,
  72  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  73  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
  74
  75static const uint edo_60ns[] =
  76{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
  77  0x00f3ec00, 0x37f7ec47, _NOT_USED_, _NOT_USED_,
  78  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
  79  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
  80  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
  81  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  82  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
  83  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  84  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
  85  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
  86  0x0cafcc00, 0x33bfcc4f, _NOT_USED_, _NOT_USED_,
  87  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  88  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
  89  0xffffcc85, 0xffffcc05, _NOT_USED_, _NOT_USED_,
  90  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  91  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
  92
  93static const uint edo_70ns[] =
  94{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
  95  0x00f3cc00, 0x37f7cc47, _NOT_USED_, _NOT_USED_,
  96  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
  97  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
  98  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
  99  0x33f7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 100  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
 101  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 102  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
 103  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
 104  0x0cafcc00, 0x33bfcc47, _NOT_USED_, _NOT_USED_,
 105  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 106  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
 107  0x7fffcc04, 0xffffcc86, 0xffffcc05, _NOT_USED_,
 108  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 109  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 110
 111#elif defined(CONFIG_DRAM_25MHZ)
 112
 113/* 25MHz tables */
 114
 115static const uint dram_60ns[] =
 116{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, _NOT_USED_,
 117  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 118  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
 119  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
 120  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
 121  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 122  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
 123  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 124  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
 125  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
 126  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 127  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 128  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
 129  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 130  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 131  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 132
 133static const uint dram_70ns[] =
 134{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
 135  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 136  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
 137  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
 138  0x08ffcc00, 0x33ffcc47, _NOT_USED_, _NOT_USED_,
 139  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 140  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, _NOT_USED_,
 141  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 142  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
 143  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
 144  0x31bfcc43, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 145  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 146  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
 147  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 148  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 149  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 150
 151static const uint edo_60ns[] =
 152{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
 153  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 154  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
 155  0x08f3cc00, 0x3ff7cc47, _NOT_USED_, _NOT_USED_,
 156  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 157  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 158  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
 159  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 160  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
 161  0x08afcc48, 0x39bfcc47, _NOT_USED_, _NOT_USED_,
 162  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 163  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 164  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
 165  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 166  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 167  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 168
 169static const uint edo_70ns[] =
 170{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
 171  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 172  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
 173  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
 174  0x3ff7cc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 175  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 176  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
 177  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 178  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
 179  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
 180  0x37bfcc47, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 181  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 182  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
 183  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 184  _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 185  0x33ffcc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 186#else
 187#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
 188#endif
 189
 190/* ------------------------------------------------------------------------- */
 191static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
 192{
 193        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 194        volatile memctl8xx_t *memctl = &immap->im_memctl;
 195
 196        /* init upm */
 197
 198        switch (delay) {
 199        case 70:
 200                if (edo) {
 201                        upmconfig (UPMA, (uint *) edo_70ns,
 202                                   sizeof (edo_70ns) / sizeof (uint));
 203                } else {
 204                        upmconfig (UPMA, (uint *) dram_70ns,
 205                                   sizeof (dram_70ns) / sizeof (uint));
 206                }
 207
 208                break;
 209
 210        case 60:
 211                if (edo) {
 212                        upmconfig (UPMA, (uint *) edo_60ns,
 213                                   sizeof (edo_60ns) / sizeof (uint));
 214                } else {
 215                        upmconfig (UPMA, (uint *) dram_60ns,
 216                                   sizeof (dram_60ns) / sizeof (uint));
 217                }
 218
 219                break;
 220
 221        default:
 222                return -1;
 223        }
 224
 225        memctl->memc_mptpr = 0x0400;    /* divide by 16 */
 226
 227        switch (noMbytes) {
 228        case 4:                         /* 4 Mbyte uses only CS2 */
 229#ifdef CONFIG_ADS
 230                memctl->memc_mamr = 0xc0a21114;
 231#else
 232                memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
 233#endif
 234                memctl->memc_or2 = 0xffc00800;  /* 4M */
 235                break;
 236
 237        case 8:                         /* 8 Mbyte uses both CS3 and CS2 */
 238                memctl->memc_mamr = 0x13a01114; /* PTA 0x13 AMA 010 */
 239                memctl->memc_or3 = 0xffc00800;  /* 4M */
 240                memctl->memc_br3 = 0x00400081 + base;
 241                memctl->memc_or2 = 0xffc00800;  /* 4M */
 242                break;
 243
 244        case 16:                        /* 16 Mbyte uses only CS2 */
 245#ifdef CONFIG_ADS       /* XXX: why PTA=0x60 only in 16M case? - NTL */
 246                memctl->memc_mamr = 0x60b21114; /* PTA 0x60 AMA 011 */
 247#else
 248                memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
 249#endif
 250                memctl->memc_or2 = 0xff000800;  /* 16M */
 251                break;
 252
 253        case 32:                        /* 32 Mbyte uses both CS3 and CS2 */
 254                memctl->memc_mamr = 0x13b01114; /* PTA 0x13 AMA 011 */
 255                memctl->memc_or3 = 0xff000800;  /* 16M */
 256                memctl->memc_br3 = 0x01000081 + base;
 257                memctl->memc_or2 = 0xff000800;  /* 16M */
 258                break;
 259
 260        default:
 261                return -1;
 262        }
 263
 264        memctl->memc_br2 = 0x81 + base; /* use upma */
 265
 266        *((uint *) BCSR1) &= ~BCSR1_DRAM_EN;    /* enable dram */
 267
 268        /* if no dimm is inserted, noMbytes is still detected as 8m, so
 269         * sanity check top and bottom of memory */
 270
 271        /* check bytes / 2 because get_ram_size tests at base+bytes, which
 272         * is not mapped */
 273        if (noMbytes == 8)
 274                if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
 275                        *((uint *) BCSR1) |= BCSR1_DRAM_EN;     /* disable dram */
 276                        return -1;
 277                }
 278
 279        return 0;
 280}
 281
 282/* ------------------------------------------------------------------------- */
 283
 284static void _dramdisable(void)
 285{
 286        volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 287        volatile memctl8xx_t *memctl = &immap->im_memctl;
 288
 289        memctl->memc_br2 = 0x00000000;
 290        memctl->memc_br3 = 0x00000000;
 291
 292        /* maybe we should turn off upma here or something */
 293}
 294#endif /* !CONFIG_MPC885ADS */
 295
 296/* ========================================================================= */
 297
 298#ifdef CONFIG_FADS /* SDRAM exists on FADS and newer boards */
 299
 300#if defined(CONFIG_SDRAM_100MHZ)
 301
 302/* ------------------------------------------------------------------------- */
 303/* sdram table by Dan Malek                                                  */
 304
 305/* This has the stretched early timing so the 50 MHz
 306 * processor can make the 100 MHz timing.  This will
 307 * work at all processor speeds.
 308 */
 309
 310#ifdef SDRAM_ALT_INIT_SEQENCE
 311# define SDRAM_MBMRVALUE0 0xc3802114 /* PTx=195,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
 312#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
 313# define SDRAM_MCRVALUE0  0x80808111   /* run upmb cs4 loop 1 addr 0x11 MRS */
 314# define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0  /* ??? why not 0x80808130? */
 315#else
 316# define SDRAM_MxMR_PTx         195
 317# define UPM_MRS_ADDR           0x11
 318# define UPM_REFRESH_ADDR       0x30    /* or 0x11 if we want to be like above? */
 319#endif /* !SDRAM_ALT_INIT_SEQUENCE */
 320
 321static const uint sdram_table[] =
 322{
 323        /* single read. (offset 0 in upm RAM) */
 324        0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
 325        0xefbbbc00, 0x1ff77c45, _NOT_USED_, _NOT_USED_,
 326
 327        /* burst read. (offset 8 in upm RAM) */
 328        0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
 329        0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
 330        0x1ff77c45,
 331
 332        /* precharge + MRS. (offset 11 in upm RAM) */
 333        0xeffbbc04, 0x1ff77c34, 0xefeabc34,
 334        0x1fb57c35, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 335
 336        /* single write. (offset 18 in upm RAM) */
 337        0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
 338        0x1ff77c45, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 339
 340        /* burst write. (offset 20 in upm RAM) */
 341        0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
 342        0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
 343        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 344        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 345
 346        /* refresh. (offset 30 in upm RAM) */
 347        0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
 348        0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
 349        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 350
 351        /* exception. (offset 3c in upm RAM) */
 352        0xeffffc06, 0x1ffffc07, _NOT_USED_, _NOT_USED_ };
 353
 354#elif defined(CONFIG_SDRAM_50MHZ)
 355
 356/* ------------------------------------------------------------------------- */
 357/* sdram table stolen from the fads manual                                   */
 358/* for chip MB811171622A-100                                                 */
 359
 360/* this table is for 32-50MHz operation */
 361#ifdef SDRAM_ALT_INIT_SEQENCE
 362# define SDRAM_MBMRVALUE0 0x80802114   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=4 */
 363# define SDRAM_MBMRVALUE1 0x80802118   /* PTx=128,PTxE,AMx=0,DSx=1,A11,RLFx=1,WLFx=1,TLFx=8 */
 364# define SDRAM_MCRVALUE0  0x80808105   /* run upmb cs4 loop 1 addr 0x5 MRS */
 365# define SDRAM_MCRVALUE1  0x80808130   /* run upmb cs4 loop 1 addr 0x30 REFRESH */
 366# define SDRAM_MPTRVALUE  0x400
 367#define SDRAM_MARVALUE   0x88
 368#else
 369# define SDRAM_MxMR_PTx         128
 370# define UPM_MRS_ADDR           0x5
 371# define UPM_REFRESH_ADDR       0x30
 372#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
 373
 374static const uint sdram_table[] =
 375{
 376        /* single read. (offset 0 in upm RAM) */
 377        0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
 378        0x1ff77c47,
 379
 380        /* precharge + MRS. (offset 5 in upm RAM) */
 381        0x1ff77c34, 0xefeabc34, 0x1fb57c35,
 382
 383        /* burst read. (offset 8 in upm RAM) */
 384        0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
 385        0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47,
 386        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 387        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 388
 389        /* single write. (offset 18 in upm RAM) */
 390        0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
 391        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 392
 393        /* burst write. (offset 20 in upm RAM) */
 394        0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
 395        0xf0affc00, 0xe1bbbc04, 0x1ff77c47, _NOT_USED_,
 396        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 397        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 398
 399        /* refresh. (offset 30 in upm RAM) */
 400        0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
 401        0xfffffc84, 0xfffffc07, _NOT_USED_, _NOT_USED_,
 402        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 403
 404        /* exception. (offset 3c in upm RAM) */
 405        0x7ffffc07, _NOT_USED_, _NOT_USED_, _NOT_USED_ };
 406
 407/* ------------------------------------------------------------------------- */
 408#else
 409#error SDRAM not correctly configured
 410#endif
 411/* ------------------------------------------------------------------------- */
 412
 413/*
 414 * Memory Periodic Timer Prescaler
 415 */
 416
 417#define SDRAM_OR4VALUE   0x00000a00 /* SAM,GL5A/S=01,addr mask or'ed on later */
 418#define SDRAM_BR4VALUE   0x000000c1 /* UPMB,base addr or'ed on later */
 419
 420/* ------------------------------------------------------------------------- */
 421#ifdef SDRAM_ALT_INIT_SEQENCE
 422/* ------------------------------------------------------------------------- */
 423
 424static int _initsdram(uint base, uint noMbytes)
 425{
 426        volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 427        volatile memctl8xx_t *memctl = &immap->im_memctl;
 428
 429        upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
 430
 431        memctl->memc_mptpr = SDRAM_MPTPRVALUE;
 432
 433        /* Configure the refresh (mostly).  This needs to be
 434        * based upon processor clock speed and optimized to provide
 435        * the highest level of performance.  For multiple banks,
 436        * this time has to be divided by the number of banks.
 437        * Although it is not clear anywhere, it appears the
 438        * refresh steps through the chip selects for this UPM
 439        * on each refresh cycle.
 440        * We have to be careful changing
 441        * UPM registers after we ask it to run these commands.
 442        */
 443
 444        memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
 445        memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */
 446
 447        udelay(200);
 448
 449        /* Now run the precharge/nop/mrs commands.
 450        */
 451
 452        memctl->memc_mcr = 0x80808111;   /* run umpb cs4 1 count 1, addr 0x11 ??? (50MHz) */
 453                                         /* run umpb cs4 1 count 1, addr 0x11 precharge+MRS (100MHz) */
 454        udelay(200);
 455
 456        /* Run 8 refresh cycles */
 457
 458        memctl->memc_mcr = SDRAM_MCRVALUE0; /* run upmb cs4 loop 1 addr 0x5 precharge+MRS (50 MHz)*/
 459                                            /* run upmb cs4 loop 1 addr 0x11 precharge+MRS (100MHz) */
 460
 461        udelay(200);
 462
 463        memctl->memc_mbmr = SDRAM_MBMRVALUE1; /* TLF 4 (100 MHz) or TLF 8 (50MHz) */
 464        memctl->memc_mcr = SDRAM_MCRVALUE1; /* run upmb cs4 loop 1 addr 0x30 refr (50 MHz) */
 465                                            /* run upmb cs4 loop 1 addr 0x11 precharge+MRS ??? (100MHz) */
 466
 467        udelay(200);
 468
 469        memctl->memc_mbmr = SDRAM_MBMRVALUE0;   /* TLF 4 */
 470
 471        memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
 472        memctl->memc_br4 = SDRAM_BR4VALUE | base;
 473
 474        return 0;
 475}
 476
 477/* ------------------------------------------------------------------------- */
 478#else  /* !SDRAM_ALT_INIT_SEQUENCE */
 479/* ------------------------------------------------------------------------- */
 480
 481/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 482# define MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 483# define MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 484
 485/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 486# define MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 487# define MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 488
 489/*
 490 * MxMR settings for SDRAM
 491 */
 492
 493/* 8 column SDRAM */
 494# define SDRAM_MxMR_8COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTBE  |   \
 495                        MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
 496                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 497/* 9 column SDRAM */
 498# define SDRAM_MxMR_9COL ((SDRAM_MxMR_PTx << MBMR_PTB_SHIFT)  | MBMR_PTAE  |   \
 499                        MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
 500                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 501
 502static int _initsdram(uint base, uint noMbytes)
 503{
 504        volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 505        volatile memctl8xx_t *memctl = &immap->im_memctl;
 506
 507        upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
 508
 509        memctl->memc_mptpr = MPTPR_2BK_4K;
 510        memctl->memc_mbmr  = SDRAM_MxMR_8COL & (~(MBMR_PTBE)); /* no refresh yet */
 511
 512        /* map CS 4 */
 513        memctl->memc_or4 = SDRAM_OR4VALUE | ~((noMbytes<<20)-1);
 514        memctl->memc_br4 = SDRAM_BR4VALUE | base;
 515
 516        /* Perform SDRAM initilization */
 517# ifdef UPM_NOP_ADDR    /* not currently in UPM table */
 518        /* step 1: nop */
 519        memctl->memc_mar = 0x00000000;
 520        memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
 521                           MCR_MLCF(0) | UPM_NOP_ADDR;
 522# endif
 523
 524        /* step 2: delay */
 525        udelay(200);
 526
 527# ifdef UPM_PRECHARGE_ADDR /* merged with MRS in UPM table */
 528        /* step 3: precharge */
 529        memctl->memc_mar = 0x00000000;
 530        memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
 531                           MCR_MLCF(4) | UPM_PRECHARGE_ADDR;
 532# endif
 533
 534        /* step 4: refresh */
 535        memctl->memc_mar = 0x00000000;
 536        memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
 537                           MCR_MLCF(2) | UPM_REFRESH_ADDR;
 538
 539        /*
 540         * note: for some reason, the UPM values we are using include
 541         * precharge with MRS
 542         */
 543
 544        /* step 5: mrs */
 545        memctl->memc_mar = 0x00000088;
 546        memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
 547                           MCR_MLCF(1) | UPM_MRS_ADDR;
 548
 549# ifdef UPM_NOP_ADDR
 550        memctl->memc_mar = 0x00000000;
 551        memctl->memc_mcr = MCR_UPM_B | MCR_OP_RUN | MCR_MB_CS4 |
 552                           MCR_MLCF(0) | UPM_NOP_ADDR;
 553# endif
 554        /*
 555         * Enable refresh
 556         */
 557
 558        memctl->memc_mbmr |= MBMR_PTBE;
 559        return 0;
 560}
 561#endif  /* !SDRAM_ALT_INIT_SEQUENCE */
 562
 563/* ------------------------------------------------------------------------- */
 564
 565static void _sdramdisable(void)
 566{
 567        volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 568        volatile memctl8xx_t *memctl = &immap->im_memctl;
 569
 570        memctl->memc_br4 = 0x00000000;
 571
 572        /* maybe we should turn off upmb here or something */
 573}
 574
 575/* ------------------------------------------------------------------------- */
 576
 577static int initsdram(uint base, uint *noMbytes)
 578{
 579        uint m = CONFIG_SYS_SDRAM_SIZE>>20;
 580
 581        /* _initsdram needs access to sdram */
 582        *((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
 583
 584        if(!_initsdram(base, m))
 585        {
 586                *noMbytes += m;
 587                return 0;
 588        }
 589        else
 590        {
 591                *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
 592
 593                _sdramdisable();
 594
 595                return -1;
 596        }
 597}
 598
 599#endif /* CONFIG_FADS */
 600
 601/* ========================================================================= */
 602
 603phys_size_t initdram (int board_type)
 604{
 605        uint sdramsz = 0;       /* size of sdram in Mbytes */
 606        uint m = 0;             /* size of dram in Mbytes */
 607#ifndef CONFIG_MPC885ADS
 608        uint base = 0;          /* base of dram in bytes */
 609        uint k, s;
 610#endif
 611
 612#ifdef CONFIG_FADS
 613        if (!initsdram (0x00000000, &sdramsz)) {
 614#ifndef CONFIG_MPC885ADS
 615                base = sdramsz << 20;
 616#endif
 617                printf ("(%u MB SDRAM) ", sdramsz);
 618        }
 619#endif
 620#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */
 621        k = (*((uint *) BCSR2) >> 23) & 0x0f;
 622
 623        switch (k & 0x3) {
 624                /* "MCM36100 / MT8D132X" */
 625        case 0x00:
 626                m = 4;
 627                break;
 628
 629                /* "MCM36800 / MT16D832X" */
 630        case 0x01:
 631                m = 32;
 632                break;
 633                /* "MCM36400 / MT8D432X" */
 634        case 0x02:
 635                m = 16;
 636                break;
 637                /* "MCM36200 / MT16D832X ?" */
 638        case 0x03:
 639                m = 8;
 640                break;
 641
 642        }
 643
 644        switch (k >> 2) {
 645        case 0x02:
 646                k = 70;
 647                break;
 648
 649        case 0x03:
 650                k = 60;
 651                break;
 652
 653        default:
 654                printf ("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
 655                k = 70;
 656        }
 657
 658#ifdef CONFIG_FADS
 659        /* the FADS is missing this bit, all rams treated as non-edo */
 660        s = 0;
 661#else
 662        s = (*((uint *) BCSR2) >> 27) & 0x01;
 663#endif
 664
 665        if (!_draminit (base, m, s, k)) {
 666                printf ("%dM %dns %sDRAM: ", m, k, s ? "EDO " : "");
 667        } else {
 668                _dramdisable ();
 669                m = 0;
 670        }
 671#endif /* !CONFIG_MPC885ADS */
 672        m += sdramsz;                           /* add sdram size to total */
 673
 674        return (m << 20);
 675}
 676
 677/* ------------------------------------------------------------------------- */
 678
 679int testdram (void)
 680{
 681    /* TODO: XXX XXX XXX */
 682    printf ("test: 16 MB - ok\n");
 683
 684    return (0);
 685}
 686
 687/* ========================================================================= */
 688
 689/*
 690 * Check Board Identity:
 691 */
 692
 693#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD)
 694static void checkdboard(void)
 695{
 696        /* get db type from BCSR 3 */
 697        uint k = (*((uint *)BCSR3) >> 24) & 0x3f;
 698
 699        puts (" with db ");
 700
 701        switch(k) {
 702        case 0x03 :
 703                puts ("MPC823");
 704                break;
 705        case 0x20 :
 706                puts ("MPC801");
 707                break;
 708        case 0x21 :
 709                puts ("MPC850");
 710                break;
 711        case 0x22 :
 712                puts ("MPC821, MPC860 / MPC860SAR / MPC860T");
 713                break;
 714        case 0x23 :
 715                puts ("MPC860SAR");
 716                break;
 717        case 0x24 :
 718        case 0x2A :
 719                puts ("MPC860T");
 720                break;
 721        case 0x3F :
 722                puts ("MPC850SAR");
 723                break;
 724        default : printf("0x%x", k);
 725        }
 726}
 727#endif  /* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */
 728
 729int checkboard (void)
 730{
 731#if   defined(CONFIG_MPC86xADS)
 732        puts ("Board: MPC86xADS\n");
 733#elif defined(CONFIG_MPC885ADS)
 734        puts ("Board: MPC885ADS\n");
 735#else /* Only old ADS/FADS have got revision ID in BCSR3 */
 736        uint r =  (((*((uint *) BCSR3) >> 23) & 1) << 3)
 737                | (((*((uint *) BCSR3) >> 19) & 1) << 2)
 738                | (((*((uint *) BCSR3) >> 16) & 3));
 739
 740        puts ("Board: ");
 741#if defined(CONFIG_FADS)
 742        puts ("FADS");
 743        checkdboard ();
 744#else
 745        puts ("ADS");
 746#endif
 747
 748        puts (" rev ");
 749
 750        switch (r) {
 751#if defined(CONFIG_ADS)
 752        case 0x00:
 753                puts ("ENG - this board sucks, check the errata, not supported\n");
 754                return -1;
 755        case 0x01:
 756                puts ("PILOT - warning, read errata \n");
 757                break;
 758        case 0x02:
 759                puts ("A - warning, read errata \n");
 760                break;
 761        case 0x03:
 762                puts ("B\n");
 763                break;
 764#else  /* FADS */
 765        case 0x00:
 766                puts ("ENG\n");
 767                break;
 768        case 0x01:
 769                puts ("PILOT\n");
 770                break;
 771#endif /* CONFIG_ADS */
 772        default:
 773                printf ("unknown (0x%x)\n", r);
 774                return -1;
 775        }
 776#endif /* CONFIG_MPC86xADS */
 777
 778        return 0;
 779}
 780
 781/* ========================================================================= */
 782
 783#if defined(CONFIG_CMD_PCMCIA)
 784
 785#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
 786volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
 787#endif
 788
 789int pcmcia_init(void)
 790{
 791        volatile pcmconf8xx_t   *pcmp;
 792        uint v, slota = 0, slotb = 0;
 793
 794        /*
 795        ** Enable the PCMCIA for a Flash card.
 796        */
 797        pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 798
 799#if 0
 800        pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
 801        pcmp->pcmc_por0 = 0xc00ff05d;
 802#endif
 803
 804        /* Set all slots to zero by default. */
 805        pcmp->pcmc_pgcra = 0;
 806        pcmp->pcmc_pgcrb = 0;
 807#ifdef CONFIG_PCMCIA_SLOT_A
 808        pcmp->pcmc_pgcra = 0x40;
 809#endif
 810#ifdef CONFIG_PCMCIA_SLOT_B
 811        pcmp->pcmc_pgcrb = 0x40;
 812#endif
 813
 814        /* enable PCMCIA buffers */
 815        *((uint *)BCSR1) &= ~BCSR1_PCCEN;
 816
 817        /* Check if any PCMCIA card is plugged in. */
 818
 819#ifdef CONFIG_PCMCIA_SLOT_A
 820        slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ;
 821#endif
 822#ifdef CONFIG_PCMCIA_SLOT_B
 823        slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ;
 824#endif
 825
 826        if (!(slota || slotb)) {
 827                printf("No card present\n");
 828                pcmp->pcmc_pgcra = 0;
 829                pcmp->pcmc_pgcrb = 0;
 830                return -1;
 831        }
 832        else
 833                printf("Card present (");
 834
 835        v = 0;
 836
 837        /* both the ADS and the FADS have a 5V keyed pcmcia connector (?)
 838        **
 839        ** Paolo - Yes, but i have to insert some 3.3V card in that slot on
 840        **         my FADS... :-)
 841        */
 842
 843#if defined(CONFIG_MPC86x)
 844        switch ((pcmp->pcmc_pipr >> 30) & 3)
 845#elif defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
 846        switch ((pcmp->pcmc_pipr >> 14) & 3)
 847#endif
 848        {
 849        case 0x03 :
 850                printf("5V");
 851                v = 5;
 852                break;
 853        case 0x01 :
 854                printf("5V and 3V");
 855#ifdef CONFIG_FADS
 856                v = 3; /* User lower voltage if supported! */
 857#else
 858                v = 5;
 859#endif
 860                break;
 861        case 0x00 :
 862                printf("5V, 3V and x.xV");
 863#ifdef CONFIG_FADS
 864                v = 3; /* User lower voltage if supported! */
 865#else
 866                v = 5;
 867#endif
 868                break;
 869        }
 870
 871        switch (v) {
 872#ifdef CONFIG_FADS
 873        case 3:
 874                printf("; using 3V");
 875                /*
 876                ** Enable 3 volt Vcc.
 877                */
 878                *((uint *)BCSR1) &= ~BCSR1_PCCVCC1;
 879                *((uint *)BCSR1) |= BCSR1_PCCVCC0;
 880                break;
 881#endif
 882        case 5:
 883                printf("; using 5V");
 884#ifdef CONFIG_ADS
 885                /*
 886                ** Enable 5 volt Vcc.
 887                */
 888                *((uint *)BCSR1) &= ~BCSR1_PCCVCCON;
 889#endif
 890#ifdef CONFIG_FADS
 891                /*
 892                ** Enable 5 volt Vcc.
 893                */
 894                *((uint *)BCSR1) &= ~BCSR1_PCCVCC0;
 895                *((uint *)BCSR1) |= BCSR1_PCCVCC1;
 896#endif
 897                break;
 898
 899        default:
 900                *((uint *)BCSR1) |= BCSR1_PCCEN;  /* disable pcmcia */
 901
 902                printf("; unknown voltage");
 903                return -1;
 904        }
 905        printf(")\n");
 906        /* disable pcmcia reset after a while */
 907
 908        udelay(20);
 909
 910#ifdef CONFIG_PCMCIA_SLOT_A
 911        pcmp->pcmc_pgcra = 0;
 912#endif
 913#ifdef CONFIG_PCMCIA_SLOT_B
 914        pcmp->pcmc_pgcrb = 0;
 915#endif
 916
 917        /* If you using a real hd you should give a short
 918        * spin-up time. */
 919#ifdef CONFIG_DISK_SPINUP_TIME
 920        udelay(CONFIG_DISK_SPINUP_TIME);
 921#endif
 922
 923        return 0;
 924}
 925
 926#endif
 927
 928/* ========================================================================= */
 929
 930#ifdef CONFIG_SYS_PC_IDE_RESET
 931
 932void ide_set_reset(int on)
 933{
 934        volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 935
 936        /*
 937         * Configure PC for IDE Reset Pin
 938         */
 939        if (on) {               /* assert RESET */
 940                immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 941        } else {                /* release RESET */
 942                immr->im_ioport.iop_pcdat |=   CONFIG_SYS_PC_IDE_RESET;
 943        }
 944
 945        /* program port pin as GPIO output */
 946        immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
 947        immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_IDE_RESET);
 948        immr->im_ioport.iop_pcdir |=   CONFIG_SYS_PC_IDE_RESET;
 949}
 950
 951#endif  /* CONFIG_SYS_PC_IDE_RESET */
 952