LXR uboot/board/freescale/m54455evb/m54455evb.c

   1/*
   2 * (C) Copyright 2000-2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <pci.h>
  29#include <asm/immap.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32
  33int checkboard(void)
  34{
  35        puts("Board: ");
  36        puts("Freescale M54455 EVB\n");
  37        return 0;
  38};
  39
  40phys_size_t initdram(int board_type)
  41{
  42        u32 dramsize;
  43#ifdef CONFIG_CF_SBF
  44        /*
  45         * Serial Boot: The dram is already initialized in start.S
  46         * only require to return DRAM size
  47         */
  48        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
  49#else
  50        volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
  51        volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
  52        u32 i;
  53
  54        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
  55
  56        for (i = 0x13; i < 0x20; i++) {
  57                if (dramsize == (1 << i))
  58                        break;
  59        }
  60        i--;
  61
  62        gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
  63
  64        sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
  65        sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
  66
  67        sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
  68        sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
  69
  70        /* Issue PALL */
  71        sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  72
  73        /* Issue LEMR */
  74        sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
  75        sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
  76
  77        udelay(500);
  78
  79        /* Issue PALL */
  80        sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  81
  82        /* Perform two refresh cycles */
  83        sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  84        sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  85
  86        sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
  87
  88        sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
  89
  90        udelay(100);
  91#endif
  92        return (dramsize << 1);
  93};
  94
  95int testdram(void)
  96{
  97        /* TODO: XXX XXX XXX */
  98        printf("DRAM test not implemented!\n");
  99
 100        return (0);
 101}
 102
 103#if defined(CONFIG_CMD_IDE)
 104#include <ata.h>
 105
 106int ide_preinit(void)
 107{
 108        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 109
 110        gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
 111        gpio->par_feci2c |=
 112            (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
 113                                           GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
 114        gpio->par_ata |=
 115            (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
 116             GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
 117             | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
 118             GPIO_PAR_ATA_IORDY_IORDY);
 119        gpio->par_pci |=
 120            (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
 121
 122        return (0);
 123}
 124
 125void ide_set_reset(int idereset)
 126{
 127        volatile atac_t *ata = (atac_t *) MMAP_ATA;
 128        long period;
 129        /*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 130        int piotms[5][9] = {
 131                {70, 165, 60, 30, 50, 5, 20, 0, 35},    /* PIO 0 */
 132                {50, 125, 45, 20, 35, 5, 15, 0, 35},    /* PIO 1 */
 133                {30, 100, 30, 15, 20, 5, 10, 0, 35},    /* PIO 2 */
 134                {30, 80, 30, 10, 20, 5, 10, 0, 35},     /* PIO 3 */
 135                {25, 70, 20, 10, 20, 5, 10, 0, 35}
 136        };                      /* PIO 4 */
 137
 138        if (idereset) {
 139                ata->cr = 0;    /* control reset */
 140                udelay(10000);
 141        } else {
 142#define CALC_TIMING(t) (t + period - 1) / period
 143                period = 1000000000 / gd->bus_clk;      /* period in ns */
 144
 145                /*ata->ton = CALC_TIMING (180); */
 146                ata->t1 = CALC_TIMING(piotms[2][0]);
 147                ata->t2w = CALC_TIMING(piotms[2][1]);
 148                ata->t2r = CALC_TIMING(piotms[2][1]);
 149                ata->ta = CALC_TIMING(piotms[2][8]);
 150                ata->trd = CALC_TIMING(piotms[2][7]);
 151                ata->t4 = CALC_TIMING(piotms[2][3]);
 152                ata->t9 = CALC_TIMING(piotms[2][6]);
 153
 154                ata->cr = 0x40; /* IORDY enable */
 155                udelay(200000);
 156                ata->cr |= 0x01;        /* IORDY enable */
 157        }
 158}
 159#endif
 160
 161#if defined(CONFIG_PCI)
 162/*
 163 * Initialize PCI devices, report devices found.
 164 */
 165static struct pci_controller hose;
 166extern void pci_mcf5445x_init(struct pci_controller *hose);
 167
 168void pci_init_board(void)
 169{
 170        pci_mcf5445x_init(&hose);
 171}
 172#endif                          /* CONFIG_PCI */
 173
 174#if defined(CONFIG_FLASH_CFI_LEGACY)
 175#include <flash.h>
 176ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 177{
 178        int sect[] = CONFIG_SYS_ATMEL_SECT;
 179        int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
 180        int i, j, k;
 181
 182        if (base != CONFIG_SYS_ATMEL_BASE)
 183                return 0;
 184
 185        info->flash_id          = 0x01000000;
 186        info->portwidth         = 1;
 187        info->chipwidth         = 1;
 188        info->buffer_size       = 1;
 189        info->erase_blk_tout    = 16384;
 190        info->write_tout        = 2;
 191        info->buffer_write_tout = 5;
 192        info->vendor            = 0xFFF0; /* CFI_CMDSET_AMD_LEGACY */
 193        info->cmd_reset         = 0x00F0;
 194        info->interface         = FLASH_CFI_X8;
 195        info->legacy_unlock     = 0;
 196        info->manufacturer_id   = (u16) ATM_MANUFACT;
 197        info->device_id         = ATM_ID_LV040;
 198        info->device_id2        = 0;
 199
 200        info->ext_addr          = 0;
 201        info->cfi_version       = 0x3133;
 202        info->cfi_offset        = 0x0000;
 203        info->addr_unlock1      = 0x00000555;
 204        info->addr_unlock2      = 0x000002AA;
 205        info->name              = "CFI conformant";
 206
 207        info->size              = 0;
 208        info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
 209        info->start[0] = base;
 210        for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
 211                info->size += sect[i] * sectsz[i];
 212
 213                for (j = 0; j < sect[i]; j++, k++) {
 214                        info->start[k + 1] = info->start[k] + sectsz[i];
 215                        info->protect[k] = 0;
 216                }
 217        }
 218
 219        return 1;
 220}
 221#endif                          /* CONFIG_SYS_FLASH_CFI */
 222