LXR uboot/board/micronas/vct/vcth/reg

   1/*
   2 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
   3 *
   4 * Copyright (C) 2006 Micronas GmbH
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License as
   8 * published by the Free Software Foundation; either version 2 of
   9 * the License, or (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 * MA 02111-1307 USA
  20 */
  21
  22#ifndef _REG_SCC_PREMIUM_H_
  23#define _REG_SCC_PREMIUM_H_
  24
  25#define SCC0_BASE               0x00110000
  26#define SCC1_BASE               0x00110080
  27#define SCC2_BASE               0x00110100
  28#define SCC3_BASE               0x00110180
  29#define SCC4_BASE               0x00110200
  30#define SCC5_BASE               0x00110280
  31#define SCC6_BASE               0x00110300
  32#define SCC7_BASE               0x00110380
  33#define SCC8_BASE               0x00110400
  34#define SCC9_BASE               0x00110480
  35#define SCC10_BASE              0x00110500
  36#define SCC11_BASE              0x00110580
  37#define SCC12_BASE              0x00110600
  38#define SCC13_BASE              0x00110680
  39#define SCC14_BASE              0x00110700
  40#define SCC15_BASE              0x00110780
  41#define SCC16_BASE              0x00110800
  42#define SCC17_BASE              0x00110880
  43#define SCC18_BASE              0x00110900
  44#define SCC19_BASE              0x00110980
  45#define SCC20_BASE              0x00110a00
  46#define SCC21_BASE              0x00110a80
  47#define SCC22_BASE              0x00110b00
  48#define SCC23_BASE              0x00110b80
  49#define SCC24_BASE              0x00110c00
  50#define SCC25_BASE              0x00110c80
  51#define SCC26_BASE              0x00110d00
  52#define SCC27_BASE              0x00110d80
  53#define SCC28_BASE              0x00110e00
  54#define SCC29_BASE              0x00110e80
  55#define SCC30_BASE              0x00110f00
  56#define SCC31_BASE              0x00110f80
  57#define SCC32_BASE              0x00111000
  58#define SCC33_BASE              0x00111080
  59#define SCC34_BASE              0x00111100
  60#define SCC35_BASE              0x00111180
  61#define SCC36_BASE              0x00111200
  62#define SCC37_BASE              0x00111280
  63#define SCC38_BASE              0x00111300
  64#define SCC39_BASE              0x00111380
  65#define SCC40_BASE              0x00111400
  66
  67/*  Relative offsets of the register adresses */
  68
  69#define SCC_ENABLE_OFFS         0x00000000
  70#define SCC_ENABLE(base)        ((base) + SCC_ENABLE_OFFS)
  71#define SCC_RESET_OFFS          0x00000004
  72#define SCC_RESET(base)         ((base) + SCC_RESET_OFFS)
  73#define SCC_VCID_OFFS           0x00000008
  74#define SCC_VCID(base)          ((base) + SCC_VCID_OFFS)
  75#define SCC_MCI_CFG_OFFS        0x0000000C
  76#define SCC_MCI_CFG(base)       ((base) + SCC_MCI_CFG_OFFS)
  77#define SCC_PACKET_CFG1_OFFS    0x00000010
  78#define SCC_PACKET_CFG1(base)   ((base) + SCC_PACKET_CFG1_OFFS)
  79#define SCC_PACKET_CFG2_OFFS    0x00000014
  80#define SCC_PACKET_CFG2(base)   ((base) + SCC_PACKET_CFG2_OFFS)
  81#define SCC_PACKET_CFG3_OFFS    0x00000018
  82#define SCC_PACKET_CFG3(base)   ((base) + SCC_PACKET_CFG3_OFFS)
  83#define SCC_DMA_CFG_OFFS        0x0000001C
  84#define SCC_DMA_CFG(base)       ((base) + SCC_DMA_CFG_OFFS)
  85#define SCC_CMD_OFFS            0x00000020
  86#define SCC_CMD(base)           ((base) + SCC_CMD_OFFS)
  87#define SCC_PRIO_OFFS           0x00000024
  88#define SCC_PRIO(base)          ((base) + SCC_PRIO_OFFS)
  89#define SCC_DEBUG_OFFS          0x00000028
  90#define SCC_DEBUG(base)         ((base) + SCC_DEBUG_OFFS)
  91#define SCC_STATUS_OFFS         0x0000002C
  92#define SCC_STATUS(base)        ((base) + SCC_STATUS_OFFS)
  93#define SCC_IMR_OFFS            0x00000030
  94#define SCC_IMR(base)           ((base) + SCC_IMR_OFFS)
  95#define SCC_ISR_OFFS            0x00000034
  96#define SCC_ISR(base)           ((base) + SCC_ISR_OFFS)
  97#define SCC_DMA_OFFSET_OFFS     0x00000038
  98#define SCC_DMA_OFFSET(base)    ((base) + SCC_DMA_OFFSET_OFFS)
  99#define SCC_RS_CTLSTS_OFFS      0x0000003C
 100#define SCC_RS_CTLSTS(base)     ((base) + SCC_RS_CTLSTS_OFFS)
 101
 102#endif
 103