LXR uboot/board/netta/netta.c

   1/*
   2 * (C) Copyright 2000-2004
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
  26 * U-Boot port on NetTA4 board
  27 */
  28
  29#include <common.h>
  30#include <miiphy.h>
  31
  32#include "mpc8xx.h"
  33
  34#ifdef CONFIG_HW_WATCHDOG
  35#include <watchdog.h>
  36#endif
  37
  38int fec8xx_miiphy_read(char *devname, unsigned char addr,
  39                unsigned char  reg, unsigned short *value);
  40int fec8xx_miiphy_write(char *devname, unsigned char  addr,
  41                unsigned char  reg, unsigned short value);
  42
  43/****************************************************************/
  44
  45/* some sane bit macros */
  46#define _BD(_b)                         (1U << (31-(_b)))
  47#define _BDR(_l, _h)                    (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
  48
  49#define _BW(_b)                         (1U << (15-(_b)))
  50#define _BWR(_l, _h)                    (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
  51
  52#define _BB(_b)                         (1U << (7-(_b)))
  53#define _BBR(_l, _h)                    (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
  54
  55#define _B(_b)                          _BD(_b)
  56#define _BR(_l, _h)                     _BDR(_l, _h)
  57
  58/****************************************************************/
  59
  60/*
  61 * Check Board Identity:
  62 *
  63 * Return 1 always.
  64 */
  65
  66int checkboard(void)
  67{
  68        printf ("Intracom NETTA"
  69#if defined(CONFIG_NETTA_ISDN)
  70                        " with ISDN support"
  71#endif
  72#if defined(CONFIG_NETTA_6412)
  73                        " (DSP:TI6412)"
  74#else
  75                        " (DSP:TI6711)"
  76#endif
  77                        "\n"
  78                        );
  79        return (0);
  80}
  81
  82/****************************************************************/
  83
  84#define _NOT_USED_      0xFFFFFFFF
  85
  86/****************************************************************/
  87
  88#define CS_0000         0x00000000
  89#define CS_0001         0x10000000
  90#define CS_0010         0x20000000
  91#define CS_0011         0x30000000
  92#define CS_0100         0x40000000
  93#define CS_0101         0x50000000
  94#define CS_0110         0x60000000
  95#define CS_0111         0x70000000
  96#define CS_1000         0x80000000
  97#define CS_1001         0x90000000
  98#define CS_1010         0xA0000000
  99#define CS_1011         0xB0000000
 100#define CS_1100         0xC0000000
 101#define CS_1101         0xD0000000
 102#define CS_1110         0xE0000000
 103#define CS_1111         0xF0000000
 104
 105#define BS_0000         0x00000000
 106#define BS_0001         0x01000000
 107#define BS_0010         0x02000000
 108#define BS_0011         0x03000000
 109#define BS_0100         0x04000000
 110#define BS_0101         0x05000000
 111#define BS_0110         0x06000000
 112#define BS_0111         0x07000000
 113#define BS_1000         0x08000000
 114#define BS_1001         0x09000000
 115#define BS_1010         0x0A000000
 116#define BS_1011         0x0B000000
 117#define BS_1100         0x0C000000
 118#define BS_1101         0x0D000000
 119#define BS_1110         0x0E000000
 120#define BS_1111         0x0F000000
 121
 122#define A10_AAAA        0x00000000
 123#define A10_AAA0        0x00200000
 124#define A10_AAA1        0x00300000
 125#define A10_000A        0x00800000
 126#define A10_0000        0x00A00000
 127#define A10_0001        0x00B00000
 128#define A10_111A        0x00C00000
 129#define A10_1110        0x00E00000
 130#define A10_1111        0x00F00000
 131
 132#define RAS_0000        0x00000000
 133#define RAS_0001        0x00040000
 134#define RAS_1110        0x00080000
 135#define RAS_1111        0x000C0000
 136
 137#define CAS_0000        0x00000000
 138#define CAS_0001        0x00010000
 139#define CAS_1110        0x00020000
 140#define CAS_1111        0x00030000
 141
 142#define WE_0000         0x00000000
 143#define WE_0001         0x00004000
 144#define WE_1110         0x00008000
 145#define WE_1111         0x0000C000
 146
 147#define GPL4_0000       0x00000000
 148#define GPL4_0001       0x00001000
 149#define GPL4_1110       0x00002000
 150#define GPL4_1111       0x00003000
 151
 152#define GPL5_0000       0x00000000
 153#define GPL5_0001       0x00000400
 154#define GPL5_1110       0x00000800
 155#define GPL5_1111       0x00000C00
 156#define LOOP            0x00000080
 157
 158#define EXEN            0x00000040
 159
 160#define AMX_COL         0x00000000
 161#define AMX_ROW         0x00000020
 162#define AMX_MAR         0x00000030
 163
 164#define NA              0x00000008
 165
 166#define UTA             0x00000004
 167
 168#define TODT            0x00000002
 169
 170#define LAST            0x00000001
 171
 172/* #define CAS_LATENCY  3 */
 173#define CAS_LATENCY     2
 174
 175const uint sdram_table[0x40] = {
 176
 177#if CAS_LATENCY == 3
 178        /* RSS */
 179        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 180        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 181        CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 182        CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 183        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 184        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 185        _NOT_USED_, _NOT_USED_,
 186
 187        /* RBS */
 188        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 189        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 190        CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 191        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 192        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 193        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 194        CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,                         /* PALL  */
 195        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,           /* NOP   */
 196        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 197        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 198
 199        /* WSS */
 200        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 201        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 202        CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 203        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 204        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 205        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 206
 207        /* WBS */
 208        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 209        CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 210        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL,                         /* WRITE */
 211        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 212        CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 213        CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 214        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 215        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA,                   /* PALL  */
 216        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 217        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 218        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 219#endif
 220
 221#if CAS_LATENCY == 2
 222        /* RSS */
 223        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 224        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 225        CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 226        CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 227        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 228        _NOT_USED_,
 229        _NOT_USED_, _NOT_USED_,
 230
 231        /* RBS */
 232        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 233        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 234        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA,                   /* READ  */
 235        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 236        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 237        CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 238        CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL,                         /* NOP   */
 239        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 240        _NOT_USED_,
 241        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 242        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 243
 244        /* WSS */
 245        CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 246        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 247        CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA,                   /* WRITE */
 248        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 249        _NOT_USED_,
 250        _NOT_USED_, _NOT_USED_,
 251        _NOT_USED_,
 252
 253        /* WBS */
 254        CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* ACT   */
 255        CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL,                         /* NOP   */
 256        CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL,                         /* WRITE */
 257        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 258        CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,                         /* NOP   */
 259        CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA,                   /* NOP   */
 260        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,     /* PALL  */
 261        _NOT_USED_,
 262        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 263        _NOT_USED_, _NOT_USED_, _NOT_USED_,
 264        _NOT_USED_, _NOT_USED_,
 265
 266#endif
 267
 268        /* UPT */
 269        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP,            /* ATRFR */
 270        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 271        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 272        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA,                   /* NOP   */
 273        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP,            /* NOP   */
 274        CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST,     /* NOP   */
 275        _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
 276        _NOT_USED_, _NOT_USED_,
 277
 278        /* EXC */
 279        CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
 280        _NOT_USED_,
 281
 282        /* REG */
 283        CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
 284        CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
 285};
 286
 287/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
 288/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
 289#define MAR_SDRAM_INIT          ((CAS_LATENCY << 6) | 0x00000008LU)
 290
 291/* 8 */
 292#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 293                         MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 294                         MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 295
 296void check_ram(unsigned int addr, unsigned int size)
 297{
 298        unsigned int i, j, v, vv;
 299        volatile unsigned int *p;
 300        unsigned int pv;
 301
 302        p = (unsigned int *)addr;
 303        pv = (unsigned int)p;
 304        for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
 305                *p++ = pv;
 306
 307        p = (unsigned int *)addr;
 308        for (i = 0; i < size / sizeof(unsigned int); i++) {
 309                v = (unsigned int)p;
 310                vv = *p;
 311                if (vv != v) {
 312                        printf("%p: read %08x instead of %08x\n", p, vv, v);
 313                        hang();
 314                }
 315                p++;
 316        }
 317
 318        for (j = 0; j < 5; j++) {
 319                switch (j) {
 320                        case 0: v = 0x00000000; break;
 321                        case 1: v = 0xffffffff; break;
 322                        case 2: v = 0x55555555; break;
 323                        case 3: v = 0xaaaaaaaa; break;
 324                        default:v = 0xdeadbeef; break;
 325                }
 326                p = (unsigned int *)addr;
 327                for (i = 0; i < size / sizeof(unsigned int); i++) {
 328                        *p = v;
 329                        vv = *p;
 330                        if (vv != v) {
 331                                printf("%p: read %08x instead of %08x\n", p, vv, v);
 332                                hang();
 333                        }
 334                        *p = ~v;
 335                        p++;
 336                }
 337        }
 338}
 339
 340phys_size_t initdram(int board_type)
 341{
 342        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 343        volatile memctl8xx_t *memctl = &immap->im_memctl;
 344        long int size;
 345
 346        upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
 347
 348        /*
 349         * Preliminary prescaler for refresh
 350         */
 351        memctl->memc_mptpr = MPTPR_PTP_DIV8;
 352
 353        memctl->memc_mar = MAR_SDRAM_INIT;      /* 32-bit address to be output on the address bus if AMX = 0b11 */
 354
 355        /*
 356         * Map controller bank 3 to the SDRAM bank at preliminary address.
 357         */
 358        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
 359        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 360
 361        memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;       /* no refresh yet */
 362
 363        udelay(200);
 364
 365        /* perform SDRAM initialisation sequence */
 366        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C);   /* precharge all                */
 367        udelay(1);
 368
 369        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30);   /* refresh 2 times(0)           */
 370        udelay(1);
 371
 372        memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E);   /* exception program (write mar)*/
 373        udelay(1);
 374
 375        memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
 376
 377        udelay(10000);
 378
 379        {
 380                u32 d1, d2;
 381
 382                d1 = 0xAA55AA55;
 383                *(volatile u32 *)0 = d1;
 384                d2 = *(volatile u32 *)0;
 385                if (d1 != d2) {
 386                        printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 387                        hang();
 388                }
 389
 390                d1 = 0x55AA55AA;
 391                *(volatile u32 *)0 = d1;
 392                d2 = *(volatile u32 *)0;
 393                if (d1 != d2) {
 394                        printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
 395                        hang();
 396                }
 397        }
 398
 399        size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
 400
 401#if 0
 402        printf("check 0\n");
 403        check_ram(( 0 << 20), (2 << 20));
 404        printf("check 16\n");
 405        check_ram((16 << 20), (2 << 20));
 406        printf("check 32\n");
 407        check_ram((32 << 20), (2 << 20));
 408        printf("check 48\n");
 409        check_ram((48 << 20), (2 << 20));
 410#endif
 411
 412        if (size == 0) {
 413                printf("SIZE is zero: LOOP on 0\n");
 414                for (;;) {
 415                        *(volatile u32 *)0 = 0;
 416                        (void)*(volatile u32 *)0;
 417                }
 418        }
 419
 420        return size;
 421}
 422
 423/* ------------------------------------------------------------------------- */
 424
 425int misc_init_r(void)
 426{
 427        return(0);
 428}
 429
 430void reset_phys(void)
 431{
 432        int phyno;
 433        unsigned short v;
 434
 435        /* reset the damn phys */
 436        mii_init();
 437
 438        for (phyno = 0; phyno < 32; ++phyno) {
 439                fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
 440                if (v == 0xFFFF)
 441                        continue;
 442                fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
 443                udelay(10000);
 444                fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
 445                                BMCR_RESET | BMCR_ANENABLE);
 446                udelay(10000);
 447        }
 448}
 449
 450extern int board_dsp_reset(void);
 451
 452int last_stage_init(void)
 453{
 454        int r;
 455
 456        reset_phys();
 457        r = board_dsp_reset();
 458        if (r < 0)
 459                printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
 460        return 0;
 461}
 462
 463/* ------------------------------------------------------------------------- */
 464
 465/* GP = general purpose, SP = special purpose (on chip peripheral) */
 466
 467/* bits that can have a special purpose or can be configured as inputs/outputs */
 468#define PA_GP_INMASK    (_BWR(3) | _BWR(7, 9) | _BW(11))
 469#define PA_GP_OUTMASK   (_BW(6) | _BW(10) | _BWR(12, 15))
 470#define PA_SP_MASK      (_BWR(0, 2) | _BWR(4, 5))
 471#define PA_ODR_VAL      0
 472#define PA_GP_OUTVAL    (_BW(13) | _BWR(14, 15))
 473#define PA_SP_DIRVAL    0
 474
 475#define PB_GP_INMASK    (_B(28) | _B(31))
 476#define PB_GP_OUTMASK   (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
 477#define PB_SP_MASK      (_BR(22, 25))
 478#define PB_ODR_VAL      0
 479#define PB_GP_OUTVAL    (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
 480#define PB_SP_DIRVAL    0
 481
 482#define PC_GP_INMASK    (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
 483#define PC_GP_OUTMASK   (_BW(6) | _BW(12))
 484#define PC_SP_MASK      (_BW(4) | _BW(8))
 485#define PC_SOVAL        0
 486#define PC_INTVAL       _BW(7)
 487#define PC_GP_OUTVAL    (_BW(6) | _BW(12))
 488#define PC_SP_DIRVAL    0
 489
 490#define PD_GP_INMASK    0
 491#define PD_GP_OUTMASK   _BWR(3, 15)
 492#define PD_SP_MASK      0
 493
 494#if defined(CONFIG_NETTA_6412)
 495
 496#define PD_GP_OUTVAL    (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
 497
 498#else
 499
 500#define PD_GP_OUTVAL    (_BWR(5, 7) | _BW(9) | _BW(11))
 501
 502#endif
 503
 504#define PD_SP_DIRVAL    0
 505
 506int board_early_init_f(void)
 507{
 508        volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 509        volatile iop8xx_t *ioport = &immap->im_ioport;
 510        volatile cpm8xx_t *cpm = &immap->im_cpm;
 511        volatile memctl8xx_t *memctl = &immap->im_memctl;
 512
 513        /* CS1: NAND chip select */
 514        memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
 515        memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
 516#if !defined(CONFIG_NETTA_6412)
 517        /* CS2: DSP */
 518        memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
 519        memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 520#else
 521        /* CS6: DSP */
 522        memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
 523        memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
 524#endif
 525        /* CS4: External register chip select */
 526        memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
 527        memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
 528
 529        /* CS5: dummy for accurate delay */
 530        memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
 531        memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
 532
 533        ioport->iop_padat       = PA_GP_OUTVAL;
 534        ioport->iop_paodr       = PA_ODR_VAL;
 535        ioport->iop_padir       = PA_GP_OUTMASK | PA_SP_DIRVAL;
 536        ioport->iop_papar       = PA_SP_MASK;
 537
 538        cpm->cp_pbdat           = PB_GP_OUTVAL;
 539        cpm->cp_pbodr           = PB_ODR_VAL;
 540        cpm->cp_pbdir           = PB_GP_OUTMASK | PB_SP_DIRVAL;
 541        cpm->cp_pbpar           = PB_SP_MASK;
 542
 543        ioport->iop_pcdat       = PC_GP_OUTVAL;
 544        ioport->iop_pcdir       = PC_GP_OUTMASK | PC_SP_DIRVAL;
 545        ioport->iop_pcso        = PC_SOVAL;
 546        ioport->iop_pcint       = PC_INTVAL;
 547        ioport->iop_pcpar       = PC_SP_MASK;
 548
 549        ioport->iop_pddat       = PD_GP_OUTVAL;
 550        ioport->iop_pddir       = PD_GP_OUTMASK | PD_SP_DIRVAL;
 551        ioport->iop_pdpar       = PD_SP_MASK;
 552
 553        /* ioport->iop_pddat |=  (1 << (15 - 6)) | (1 << (15 - 7)); */
 554
 555        return 0;
 556}
 557
 558#if defined(CONFIG_CMD_PCMCIA)
 559
 560int pcmcia_init(void)
 561{
 562        return 0;
 563}
 564
 565#endif
 566
 567#ifdef CONFIG_HW_WATCHDOG
 568
 569void hw_watchdog_reset(void)
 570{
 571        /* XXX add here the really funky stuff */
 572}
 573
 574#endif
 575