LXR uboot/board/samsung/smdk5250/smdk5250.c

   1/*
   2 * Copyright (C) 2012 Samsung Electronics
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <common.h>
  24#include <asm/io.h>
  25#include <netdev.h>
  26#include <asm/arch/cpu.h>
  27#include <asm/arch/gpio.h>
  28#include <asm/arch/mmc.h>
  29#include <asm/arch/sromc.h>
  30
  31DECLARE_GLOBAL_DATA_PTR;
  32struct exynos5_gpio_part1 *gpio1;
  33
  34#ifdef CONFIG_SMC911X
  35static void smc9115_pre_init(void)
  36{
  37        u32 smc_bw_conf, smc_bc_conf;
  38        int i;
  39
  40        /*
  41         * SROM:CS1 and EBI
  42         *
  43         * GPY0[0]      SROM_CSn[0]
  44         * GPY0[1]      SROM_CSn[1](2)
  45         * GPY0[2]      SROM_CSn[2]
  46         * GPY0[3]      SROM_CSn[3]
  47         * GPY0[4]      EBI_OEn(2)
  48         * GPY0[5]      EBI_EEn(2)
  49         *
  50         * GPY1[0]      EBI_BEn[0](2)
  51         * GPY1[1]      EBI_BEn[1](2)
  52         * GPY1[2]      SROM_WAIT(2)
  53         * GPY1[3]      EBI_DATA_RDn(2)
  54         */
  55        s5p_gpio_cfg_pin(&gpio1->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
  56        s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2));
  57        s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2));
  58
  59        for (i = 0; i < 4; i++)
  60                s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2));
  61
  62        /*
  63         * EBI: 8 Addrss Lines
  64         *
  65         * GPY3[0]      EBI_ADDR[0](2)
  66         * GPY3[1]      EBI_ADDR[1](2)
  67         * GPY3[2]      EBI_ADDR[2](2)
  68         * GPY3[3]      EBI_ADDR[3](2)
  69         * GPY3[4]      EBI_ADDR[4](2)
  70         * GPY3[5]      EBI_ADDR[5](2)
  71         * GPY3[6]      EBI_ADDR[6](2)
  72         * GPY3[7]      EBI_ADDR[7](2)
  73         *
  74         * EBI: 16 Data Lines
  75         *
  76         * GPY5[0]      EBI_DATA[0](2)
  77         * GPY5[1]      EBI_DATA[1](2)
  78         * GPY5[2]      EBI_DATA[2](2)
  79         * GPY5[3]      EBI_DATA[3](2)
  80         * GPY5[4]      EBI_DATA[4](2)
  81         * GPY5[5]      EBI_DATA[5](2)
  82         * GPY5[6]      EBI_DATA[6](2)
  83         * GPY5[7]      EBI_DATA[7](2)
  84         *
  85         * GPY6[0]      EBI_DATA[8](2)
  86         * GPY6[1]      EBI_DATA[9](2)
  87         * GPY6[2]      EBI_DATA[10](2)
  88         * GPY6[3]      EBI_DATA[11](2)
  89         * GPY6[4]      EBI_DATA[12](2)
  90         * GPY6[5]      EBI_DATA[13](2)
  91         * GPY6[6]      EBI_DATA[14](2)
  92         * GPY6[7]      EBI_DATA[15](2)
  93         */
  94        for (i = 0; i < 8; i++) {
  95                s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2));
  96                s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP);
  97
  98                s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2));
  99                s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP);
 100
 101                s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2));
 102                s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP);
 103        }
 104
 105        /* Ethernet needs data bus width of 16 bits */
 106        smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
 107                        | SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
 108
 109        smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
 110                        | SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
 111                        | SROMC_BC_TAH(0x0C)  | SROMC_BC_TACP(0x09)
 112                        | SROMC_BC_PMC(0x01);
 113
 114        /* Select and configure the SROMC bank */
 115        s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
 116}
 117#endif
 118
 119int board_init(void)
 120{
 121        gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 122
 123        gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
 124        return 0;
 125}
 126
 127int dram_init(void)
 128{
 129        gd->ram_size    = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
 130                        + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE)
 131                        + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE)
 132                        + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)
 133                        + get_ram_size((long *)PHYS_SDRAM_5, PHYS_SDRAM_7_SIZE)
 134                        + get_ram_size((long *)PHYS_SDRAM_6, PHYS_SDRAM_7_SIZE)
 135                        + get_ram_size((long *)PHYS_SDRAM_7, PHYS_SDRAM_7_SIZE)
 136                        + get_ram_size((long *)PHYS_SDRAM_8, PHYS_SDRAM_8_SIZE);
 137        return 0;
 138}
 139
 140void dram_init_banksize(void)
 141{
 142        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 143        gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
 144                                                        PHYS_SDRAM_1_SIZE);
 145        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 146        gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
 147                                                        PHYS_SDRAM_2_SIZE);
 148        gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
 149        gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3,
 150                                                        PHYS_SDRAM_3_SIZE);
 151        gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
 152        gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4,
 153                                                        PHYS_SDRAM_4_SIZE);
 154        gd->bd->bi_dram[4].start = PHYS_SDRAM_5;
 155        gd->bd->bi_dram[4].size = get_ram_size((long *)PHYS_SDRAM_5,
 156                                                        PHYS_SDRAM_5_SIZE);
 157        gd->bd->bi_dram[5].start = PHYS_SDRAM_6;
 158        gd->bd->bi_dram[5].size = get_ram_size((long *)PHYS_SDRAM_6,
 159                                                        PHYS_SDRAM_6_SIZE);
 160        gd->bd->bi_dram[6].start = PHYS_SDRAM_7;
 161        gd->bd->bi_dram[6].size = get_ram_size((long *)PHYS_SDRAM_7,
 162                                                        PHYS_SDRAM_7_SIZE);
 163        gd->bd->bi_dram[7].start = PHYS_SDRAM_8;
 164        gd->bd->bi_dram[7].size = get_ram_size((long *)PHYS_SDRAM_8,
 165                                                        PHYS_SDRAM_8_SIZE);
 166}
 167
 168int board_eth_init(bd_t *bis)
 169{
 170#ifdef CONFIG_SMC911X
 171        smc9115_pre_init();
 172        return smc911x_initialize(0, CONFIG_SMC911X_BASE);
 173#endif
 174        return 0;
 175}
 176
 177#ifdef CONFIG_DISPLAY_BOARDINFO
 178int checkboard(void)
 179{
 180        printf("\nBoard: SMDK5250\n");
 181
 182        return 0;
 183}
 184#endif
 185
 186#ifdef CONFIG_GENERIC_MMC
 187int board_mmc_init(bd_t *bis)
 188{
 189        int i, err;
 190
 191        /*
 192         * MMC2 SD card GPIO:
 193         *
 194         * GPC2[0]      SD_2_CLK(2)
 195         * GPC2[1]      SD_2_CMD(2)
 196         * GPC2[2]      SD_2_CDn
 197         * GPC2[3:6]    SD_2_DATA[0:3](2)
 198         */
 199        for (i = 0; i < 7; i++) {
 200                /* GPC2[0:6] special function 2 */
 201                s5p_gpio_cfg_pin(&gpio1->c2, i, GPIO_FUNC(0x2));
 202
 203                /* GPK2[0:6] drv 4x */
 204                s5p_gpio_set_drv(&gpio1->c2, i, GPIO_DRV_4X);
 205
 206                /* GPK2[0:1] pull disable */
 207                if (i == 0 || i == 1) {
 208                        s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_NONE);
 209                        continue;
 210                }
 211
 212                /* GPK2[2:6] pull up */
 213                s5p_gpio_set_pull(&gpio1->c2, i, GPIO_PULL_UP);
 214        }
 215
 216        err = s5p_mmc_init(2, 4);
 217        return err;
 218}
 219#endif
 220
 221static void board_uart_init(void)
 222{
 223        struct exynos5_gpio_part1 *gpio1 =
 224                (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1();
 225        int i;
 226
 227        /*
 228         * UART0 GPIOs : GPA0CON[3:0] 0x2222
 229         * Must set CFG17 switches to select UART0 to use.
 230         */
 231        for (i = 0; i <= 3; i++) {
 232                s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
 233                s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
 234        }
 235
 236        /*
 237         * UART1 GPIOs : GPA0CON[5:4] 0x22
 238         * Must set CFG17 switches to select UART1 to use.
 239         *
 240         * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
 241         * in order to use them (so that those pins can be used for I2C).
 242         */
 243        for (i = 4; i <= 5; i++) {
 244                s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE);
 245                s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2));
 246        }
 247
 248        /*
 249         * UART2 GPIOs : GPA1CON[1:0] 0x22
 250         * Must set CFG17 switches to select UART2 to use.
 251         *
 252         * This only sets RXD/TXD, as RTS/CTS need a resistor soldered down
 253         * in order to use them (so that those pins can be used for I2C).
 254         */
 255        for (i = 0; i <= 1; i++) {
 256                s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 257                s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
 258        }
 259
 260        /*
 261         * UART3 GPIOs : GPA1CON[5:4] 0x22
 262         * Must set CFG16 switches to select UART3 to use.
 263         */
 264        for (i = 4; i <= 5; i++) {
 265                s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE);
 266                s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC(0x2));
 267        }
 268
 269        /*
 270         * There's no mux for UART4--it's internal only
 271         */
 272}
 273
 274#ifdef CONFIG_BOARD_EARLY_INIT_F
 275int board_early_init_f(void)
 276{
 277        board_uart_init();
 278        return 0;
 279}
 280#endif
 281