LXR uboot/drivers/mtd/nand/kb9202

   1/*
   2 * (C) Copyright 2006
   3 * KwikByte <kb9200_dev@kwikbyte.com>
   4 *
   5 * (C) Copyright 2009
   6 * Matthias Kaehlcke <matthias@kaehlcke.net>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <asm/io.h>
  29#include <asm/arch/AT91RM9200.h>
  30#include <asm/arch/hardware.h>
  31
  32#include <nand.h>
  33
  34/*
  35 *      hardware specific access to control-lines
  36 */
  37
  38#define MASK_ALE        (1 << 22)       /* our ALE is A22 */
  39#define MASK_CLE        (1 << 21)       /* our CLE is A21 */
  40
  41#define KB9202_NAND_NCE (1 << 28) /* EN* on D28 */
  42#define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
  43
  44#define KB9202_SMC2_NWS (1 << 2)
  45#define KB9202_SMC2_TDF (1 << 8)
  46#define KB9202_SMC2_RWSETUP (1 << 24)
  47#define KB9202_SMC2_RWHOLD (1 << 29)
  48
  49/*
  50 *      Board-specific function to access device control signals
  51 */
  52static void kb9202_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  53{
  54        struct nand_chip *this = mtd->priv;
  55
  56        if (ctrl & NAND_CTRL_CHANGE) {
  57                ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  58
  59                /* clear ALE and CLE bits */
  60                IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
  61
  62                if (ctrl & NAND_CLE)
  63                        IO_ADDR_W |= MASK_CLE;
  64
  65                if (ctrl & NAND_ALE)
  66                        IO_ADDR_W |= MASK_ALE;
  67
  68                this->IO_ADDR_W = (void *) IO_ADDR_W;
  69
  70                if (ctrl & NAND_NCE)
  71                        writel(KB9202_NAND_NCE, AT91C_PIOC_CODR);
  72                else
  73                        writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
  74        }
  75
  76        if (cmd != NAND_CMD_NONE)
  77                writeb(cmd, this->IO_ADDR_W);
  78}
  79
  80
  81/*
  82 * Board-specific function to access the device ready signal.
  83 */
  84static int kb9202_nand_ready(struct mtd_info *mtd)
  85{
  86        return readl(AT91C_PIOC_PDSR) & KB9202_NAND_BUSY;
  87}
  88
  89
  90/*
  91 * Board-specific NAND init.  Copied from include/linux/mtd/nand.h for reference.
  92 *
  93 * struct nand_chip - NAND Private Flash Chip Data
  94 * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  95 * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  96 * @hwcontrol:          [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
  97 * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  98 *                      If set to NULL no access to ready/busy is available and the ready/busy information
  99 *                      is read from the chip status register
 100 * @enable_hwecc:       [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
 101 *                      be provided if a hardware ECC is available
 102 * @eccmode:            [BOARDSPECIFIC] mode of ecc, see defines
 103 * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 104 * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 105 *                      special functionality. See the defines for further explanation
 106*/
 107/*
 108 * This routine initializes controller and GPIOs.
 109 */
 110int board_nand_init(struct nand_chip *nand)
 111{
 112        unsigned int value;
 113
 114        nand->ecc.mode = NAND_ECC_SOFT;
 115        nand->cmd_ctrl = kb9202_nand_hwcontrol;
 116        nand->dev_ready = kb9202_nand_ready;
 117
 118        /* in case running outside of bootloader */
 119        writel(1 << AT91C_ID_PIOC, AT91C_PMC_PCER);
 120
 121        /* setup nand flash access (allow ample margin) */
 122        /* 4 wait states, 1 setup, 1 hold, 1 float for 8-bit device */
 123        writel(AT91C_SMC2_WSEN | KB9202_SMC2_NWS | KB9202_SMC2_TDF |
 124                AT91C_SMC2_DBW_8 | KB9202_SMC2_RWSETUP | KB9202_SMC2_RWHOLD,
 125                AT91C_SMC_CSR3);
 126
 127        /* enable internal NAND controller */
 128        value = readl(AT91C_EBI_CSA);
 129        value |= AT91C_EBI_CS3A_SMC_SmartMedia;
 130        writel(value, AT91C_EBI_CSA);
 131
 132        /* enable SMOE/SMWE */
 133        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_ASR);
 134        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_PDR);
 135        writel(AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE, AT91C_PIOC_OER);
 136
 137        /* set NCE to high */
 138        writel(KB9202_NAND_NCE, AT91C_PIOC_SODR);
 139
 140        /* disable output on pin connected to the busy line of the NAND */
 141        writel(KB9202_NAND_BUSY, AT91C_PIOC_ODR);
 142
 143        /* enable the PIO to control NCE and BUSY */
 144        writel(KB9202_NAND_NCE | KB9202_NAND_BUSY, AT91C_PIOC_PER);
 145
 146        /* enable output for NCE */
 147        writel(KB9202_NAND_NCE, AT91C_PIOC_OER);
 148
 149        return (0);
 150}
 151