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17#include <common.h>
18#include <malloc.h>
19#include <linux/compiler.h>
20#include <linux/err.h>
21#include <asm/io.h>
22
23#define TX_NUM_DESC 1
24#define RX_NUM_DESC 32
25
26#define MAC_TIMEOUT (5*CONFIG_SYS_HZ)
27
28#define ETH_BUF_SZ 2048
29#define TX_BUF_SZ (ETH_BUF_SZ * TX_NUM_DESC)
30#define RX_BUF_SZ (ETH_BUF_SZ * RX_NUM_DESC)
31
32#define RXSTART 0x00000002
33#define TXSTART 0x00002000
34
35#define RXENABLE 0x00000004
36#define TXENABLE 0x00000008
37
38#define XGMAC_CONTROL_SPD 0x40000000
39#define XGMAC_CONTROL_SPD_MASK 0x60000000
40#define XGMAC_CONTROL_SARC 0x10000000
41#define XGMAC_CONTROL_SARK_MASK 0x18000000
42#define XGMAC_CONTROL_CAR 0x04000000
43#define XGMAC_CONTROL_CAR_MASK 0x06000000
44#define XGMAC_CONTROL_CAR_SHIFT 25
45#define XGMAC_CONTROL_DP 0x01000000
46#define XGMAC_CONTROL_WD 0x00800000
47#define XGMAC_CONTROL_JD 0x00400000
48#define XGMAC_CONTROL_JE 0x00100000
49#define XGMAC_CONTROL_LM 0x00001000
50#define XGMAC_CONTROL_IPC 0x00000400
51#define XGMAC_CONTROL_ACS 0x00000080
52#define XGMAC_CONTROL_DDIC 0x00000010
53#define XGMAC_CONTROL_TE 0x00000008
54#define XGMAC_CONTROL_RE 0x00000004
55
56#define XGMAC_DMA_BUSMODE_RESET 0x00000001
57#define XGMAC_DMA_BUSMODE_DSL 0x00000004
58#define XGMAC_DMA_BUSMODE_DSL_MASK 0x0000007c
59#define XGMAC_DMA_BUSMODE_DSL_SHIFT 2
60#define XGMAC_DMA_BUSMODE_ATDS 0x00000080
61#define XGMAC_DMA_BUSMODE_PBL_MASK 0x00003f00
62#define XGMAC_DMA_BUSMODE_PBL_SHIFT 8
63#define XGMAC_DMA_BUSMODE_FB 0x00010000
64#define XGMAC_DMA_BUSMODE_USP 0x00800000
65#define XGMAC_DMA_BUSMODE_8PBL 0x01000000
66#define XGMAC_DMA_BUSMODE_AAL 0x02000000
67
68#define XGMAC_DMA_AXIMODE_ENLPI 0x80000000
69#define XGMAC_DMA_AXIMODE_MGK 0x40000000
70#define XGMAC_DMA_AXIMODE_WROSR 0x00100000
71#define XGMAC_DMA_AXIMODE_WROSR_MASK 0x00F00000
72#define XGMAC_DMA_AXIMODE_WROSR_SHIFT 20
73#define XGMAC_DMA_AXIMODE_RDOSR 0x00010000
74#define XGMAC_DMA_AXIMODE_RDOSR_MASK 0x000F0000
75#define XGMAC_DMA_AXIMODE_RDOSR_SHIFT 16
76#define XGMAC_DMA_AXIMODE_AAL 0x00001000
77#define XGMAC_DMA_AXIMODE_BLEN256 0x00000080
78#define XGMAC_DMA_AXIMODE_BLEN128 0x00000040
79#define XGMAC_DMA_AXIMODE_BLEN64 0x00000020
80#define XGMAC_DMA_AXIMODE_BLEN32 0x00000010
81#define XGMAC_DMA_AXIMODE_BLEN16 0x00000008
82#define XGMAC_DMA_AXIMODE_BLEN8 0x00000004
83#define XGMAC_DMA_AXIMODE_BLEN4 0x00000002
84#define XGMAC_DMA_AXIMODE_UNDEF 0x00000001
85
86#define XGMAC_CORE_OMR_RTC_SHIFT 3
87#define XGMAC_CORE_OMR_RTC_MASK 0x00000018
88#define XGMAC_CORE_OMR_RTC 0x00000010
89#define XGMAC_CORE_OMR_RSF 0x00000020
90#define XGMAC_CORE_OMR_DT 0x00000040
91#define XGMAC_CORE_OMR_FEF 0x00000080
92#define XGMAC_CORE_OMR_EFC 0x00000100
93#define XGMAC_CORE_OMR_RFA_SHIFT 9
94#define XGMAC_CORE_OMR_RFA_MASK 0x00000E00
95#define XGMAC_CORE_OMR_RFD_SHIFT 12
96#define XGMAC_CORE_OMR_RFD_MASK 0x00007000
97#define XGMAC_CORE_OMR_TTC_SHIFT 16
98#define XGMAC_CORE_OMR_TTC_MASK 0x00030000
99#define XGMAC_CORE_OMR_TTC 0x00020000
100#define XGMAC_CORE_OMR_FTF 0x00100000
101#define XGMAC_CORE_OMR_TSF 0x00200000
102
103#define FIFO_MINUS_1K 0x0
104#define FIFO_MINUS_2K 0x1
105#define FIFO_MINUS_3K 0x2
106#define FIFO_MINUS_4K 0x3
107#define FIFO_MINUS_6K 0x4
108#define FIFO_MINUS_8K 0x5
109#define FIFO_MINUS_12K 0x6
110#define FIFO_MINUS_16K 0x7
111
112#define XGMAC_CORE_FLOW_PT_SHIFT 16
113#define XGMAC_CORE_FLOW_PT_MASK 0xFFFF0000
114#define XGMAC_CORE_FLOW_PT 0x00010000
115#define XGMAC_CORE_FLOW_DZQP 0x00000080
116#define XGMAC_CORE_FLOW_PLT_SHIFT 4
117#define XGMAC_CORE_FLOW_PLT_MASK 0x00000030
118#define XGMAC_CORE_FLOW_PLT 0x00000010
119#define XGMAC_CORE_FLOW_UP 0x00000008
120#define XGMAC_CORE_FLOW_RFE 0x00000004
121#define XGMAC_CORE_FLOW_TFE 0x00000002
122#define XGMAC_CORE_FLOW_FCB 0x00000001
123
124
125#define MAX_DESC_BUF_SZ (0x2000 - 8)
126
127#define RXDESC_EXT_STATUS 0x00000001
128#define RXDESC_CRC_ERR 0x00000002
129#define RXDESC_RX_ERR 0x00000008
130#define RXDESC_RX_WDOG 0x00000010
131#define RXDESC_FRAME_TYPE 0x00000020
132#define RXDESC_GIANT_FRAME 0x00000080
133#define RXDESC_LAST_SEG 0x00000100
134#define RXDESC_FIRST_SEG 0x00000200
135#define RXDESC_VLAN_FRAME 0x00000400
136#define RXDESC_OVERFLOW_ERR 0x00000800
137#define RXDESC_LENGTH_ERR 0x00001000
138#define RXDESC_SA_FILTER_FAIL 0x00002000
139#define RXDESC_DESCRIPTOR_ERR 0x00004000
140#define RXDESC_ERROR_SUMMARY 0x00008000
141#define RXDESC_FRAME_LEN_OFFSET 16
142#define RXDESC_FRAME_LEN_MASK 0x3fff0000
143#define RXDESC_DA_FILTER_FAIL 0x40000000
144
145#define RXDESC1_END_RING 0x00008000
146
147#define RXDESC_IP_PAYLOAD_MASK 0x00000003
148#define RXDESC_IP_PAYLOAD_UDP 0x00000001
149#define RXDESC_IP_PAYLOAD_TCP 0x00000002
150#define RXDESC_IP_PAYLOAD_ICMP 0x00000003
151#define RXDESC_IP_HEADER_ERR 0x00000008
152#define RXDESC_IP_PAYLOAD_ERR 0x00000010
153#define RXDESC_IPV4_PACKET 0x00000040
154#define RXDESC_IPV6_PACKET 0x00000080
155#define TXDESC_UNDERFLOW_ERR 0x00000001
156#define TXDESC_JABBER_TIMEOUT 0x00000002
157#define TXDESC_LOCAL_FAULT 0x00000004
158#define TXDESC_REMOTE_FAULT 0x00000008
159#define TXDESC_VLAN_FRAME 0x00000010
160#define TXDESC_FRAME_FLUSHED 0x00000020
161#define TXDESC_IP_HEADER_ERR 0x00000040
162#define TXDESC_PAYLOAD_CSUM_ERR 0x00000080
163#define TXDESC_ERROR_SUMMARY 0x00008000
164#define TXDESC_SA_CTRL_INSERT 0x00040000
165#define TXDESC_SA_CTRL_REPLACE 0x00080000
166#define TXDESC_2ND_ADDR_CHAINED 0x00100000
167#define TXDESC_END_RING 0x00200000
168#define TXDESC_CSUM_IP 0x00400000
169#define TXDESC_CSUM_IP_PAYLD 0x00800000
170#define TXDESC_CSUM_ALL 0x00C00000
171#define TXDESC_CRC_EN_REPLACE 0x01000000
172#define TXDESC_CRC_EN_APPEND 0x02000000
173#define TXDESC_DISABLE_PAD 0x04000000
174#define TXDESC_FIRST_SEG 0x10000000
175#define TXDESC_LAST_SEG 0x20000000
176#define TXDESC_INTERRUPT 0x40000000
177
178#define DESC_OWN 0x80000000
179#define DESC_BUFFER1_SZ_MASK 0x00001fff
180#define DESC_BUFFER2_SZ_MASK 0x1fff0000
181#define DESC_BUFFER2_SZ_OFFSET 16
182
183struct xgmac_regs {
184 u32 config;
185 u32 framefilter;
186 u32 resv_1[4];
187 u32 flow_control;
188 u32 vlantag;
189 u32 version;
190 u32 vlaninclude;
191 u32 resv_2[2];
192 u32 pacestretch;
193 u32 vlanhash;
194 u32 resv_3;
195 u32 intreg;
196 struct {
197 u32 hi;
198 u32 lo;
199 } macaddr[16];
200 u32 resv_4[0xd0];
201 u32 core_opmode;
202 u32 resv_5[0x2bf];
203 u32 busmode;
204 u32 txpoll;
205 u32 rxpoll;
206 u32 rxdesclist;
207 u32 txdesclist;
208 u32 dma_status;
209 u32 dma_opmode;
210 u32 intenable;
211 u32 resv_6[2];
212 u32 axi_mode;
213};
214
215struct xgmac_dma_desc {
216 __le32 flags;
217 __le32 buf_size;
218 __le32 buf1_addr;
219 __le32 buf2_addr;
220 __le32 ext_status;
221 __le32 res[3];
222};
223
224
225static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
226{
227 if (buf_sz > MAX_DESC_BUF_SZ)
228 p->buf_size = cpu_to_le32(MAX_DESC_BUF_SZ |
229 (buf_sz - MAX_DESC_BUF_SZ) << DESC_BUFFER2_SZ_OFFSET);
230 else
231 p->buf_size = cpu_to_le32(buf_sz);
232}
233
234static inline int desc_get_buf_len(struct xgmac_dma_desc *p)
235{
236 u32 len = le32_to_cpu(p->buf_size);
237 return (len & DESC_BUFFER1_SZ_MASK) +
238 ((len & DESC_BUFFER2_SZ_MASK) >> DESC_BUFFER2_SZ_OFFSET);
239}
240
241static inline void desc_init_rx_desc(struct xgmac_dma_desc *p, int ring_size,
242 int buf_sz)
243{
244 struct xgmac_dma_desc *end = p + ring_size - 1;
245
246 memset(p, 0, sizeof(*p) * ring_size);
247
248 for (; p <= end; p++)
249 desc_set_buf_len(p, buf_sz);
250
251 end->buf_size |= cpu_to_le32(RXDESC1_END_RING);
252}
253
254static inline void desc_init_tx_desc(struct xgmac_dma_desc *p, u32 ring_size)
255{
256 memset(p, 0, sizeof(*p) * ring_size);
257 p[ring_size - 1].flags = cpu_to_le32(TXDESC_END_RING);
258}
259
260static inline int desc_get_owner(struct xgmac_dma_desc *p)
261{
262 return le32_to_cpu(p->flags) & DESC_OWN;
263}
264
265static inline void desc_set_rx_owner(struct xgmac_dma_desc *p)
266{
267
268 p->flags = cpu_to_le32(DESC_OWN);
269}
270
271static inline void desc_set_tx_owner(struct xgmac_dma_desc *p, u32 flags)
272{
273 u32 tmpflags = le32_to_cpu(p->flags);
274 tmpflags &= TXDESC_END_RING;
275 tmpflags |= flags | DESC_OWN;
276 p->flags = cpu_to_le32(tmpflags);
277}
278
279static inline void *desc_get_buf_addr(struct xgmac_dma_desc *p)
280{
281 return (void *)le32_to_cpu(p->buf1_addr);
282}
283
284static inline void desc_set_buf_addr(struct xgmac_dma_desc *p,
285 void *paddr, int len)
286{
287 p->buf1_addr = cpu_to_le32(paddr);
288 if (len > MAX_DESC_BUF_SZ)
289 p->buf2_addr = cpu_to_le32(paddr + MAX_DESC_BUF_SZ);
290}
291
292static inline void desc_set_buf_addr_and_size(struct xgmac_dma_desc *p,
293 void *paddr, int len)
294{
295 desc_set_buf_len(p, len);
296 desc_set_buf_addr(p, paddr, len);
297}
298
299static inline int desc_get_rx_frame_len(struct xgmac_dma_desc *p)
300{
301 u32 data = le32_to_cpu(p->flags);
302 u32 len = (data & RXDESC_FRAME_LEN_MASK) >> RXDESC_FRAME_LEN_OFFSET;
303 if (data & RXDESC_FRAME_TYPE)
304 len -= 4;
305
306 return len;
307}
308
309struct calxeda_eth_dev {
310 struct xgmac_dma_desc rx_chain[RX_NUM_DESC];
311 struct xgmac_dma_desc tx_chain[TX_NUM_DESC];
312 char rxbuffer[RX_BUF_SZ];
313
314 u32 tx_currdesc;
315 u32 rx_currdesc;
316
317 struct eth_device *dev;
318} __aligned(32);
319
320
321
322
323
324
325static void init_rx_desc(struct calxeda_eth_dev *priv)
326{
327 struct xgmac_dma_desc *rxdesc = priv->rx_chain;
328 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
329 void *rxbuffer = priv->rxbuffer;
330 int i;
331
332 desc_init_rx_desc(rxdesc, RX_NUM_DESC, ETH_BUF_SZ);
333 writel((ulong)rxdesc, ®s->rxdesclist);
334
335 for (i = 0; i < RX_NUM_DESC; i++) {
336 desc_set_buf_addr(rxdesc + i, rxbuffer + (i * ETH_BUF_SZ),
337 ETH_BUF_SZ);
338 desc_set_rx_owner(rxdesc + i);
339 }
340}
341
342static void init_tx_desc(struct calxeda_eth_dev *priv)
343{
344 struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
345
346 desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
347 writel((ulong)priv->tx_chain, ®s->txdesclist);
348}
349
350static int xgmac_reset(struct eth_device *dev)
351{
352 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
353 int timeout = MAC_TIMEOUT;
354 u32 value;
355
356 value = readl(®s->config) & XGMAC_CONTROL_SPD_MASK;
357
358 writel(XGMAC_DMA_BUSMODE_RESET, ®s->busmode);
359 while ((timeout-- >= 0) &&
360 (readl(®s->busmode) & XGMAC_DMA_BUSMODE_RESET))
361 udelay(1);
362
363 writel(value, ®s->config);
364
365 return timeout;
366}
367
368static void xgmac_hwmacaddr(struct eth_device *dev)
369{
370 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
371 u32 macaddr[2];
372
373 memcpy(macaddr, dev->enetaddr, 6);
374 writel(macaddr[1], ®s->macaddr[0].hi);
375 writel(macaddr[0], ®s->macaddr[0].lo);
376}
377
378static int xgmac_init(struct eth_device *dev, bd_t * bis)
379{
380 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
381 struct calxeda_eth_dev *priv = dev->priv;
382 int value;
383
384 if (xgmac_reset(dev) < 0)
385 return -1;
386
387
388 xgmac_hwmacaddr(dev);
389
390
391 value = XGMAC_DMA_BUSMODE_ATDS |
392 (16 << XGMAC_DMA_BUSMODE_PBL_SHIFT) |
393 XGMAC_DMA_BUSMODE_FB | XGMAC_DMA_BUSMODE_AAL;
394 writel(value, ®s->busmode);
395
396 value = XGMAC_DMA_AXIMODE_AAL | XGMAC_DMA_AXIMODE_BLEN16 |
397 XGMAC_DMA_AXIMODE_BLEN8 | XGMAC_DMA_AXIMODE_BLEN4;
398 writel(value, ®s->axi_mode);
399
400
401 value = (FIFO_MINUS_12K << XGMAC_CORE_OMR_RFD_SHIFT) |
402 (FIFO_MINUS_4K << XGMAC_CORE_OMR_RFA_SHIFT) |
403 XGMAC_CORE_OMR_EFC | XGMAC_CORE_OMR_TSF | XGMAC_CORE_OMR_RSF;
404 writel(value, ®s->core_opmode);
405
406
407 value = (1024 << XGMAC_CORE_FLOW_PT_SHIFT) |
408 (1 << XGMAC_CORE_FLOW_PLT_SHIFT) |
409 XGMAC_CORE_FLOW_UP | XGMAC_CORE_FLOW_RFE | XGMAC_CORE_FLOW_TFE;
410 writel(value, ®s->flow_control);
411
412
413 init_rx_desc(priv);
414 init_tx_desc(priv);
415
416
417 priv->tx_currdesc = 0;
418 priv->rx_currdesc = 0;
419
420
421 value = readl(®s->config);
422 value &= XGMAC_CONTROL_SPD_MASK;
423 value |= XGMAC_CONTROL_DDIC | XGMAC_CONTROL_ACS |
424 XGMAC_CONTROL_IPC | XGMAC_CONTROL_CAR;
425
426
427 value |= RXENABLE | TXENABLE;
428 writel(value, ®s->config);
429
430 value = readl(®s->dma_opmode);
431 value |= RXSTART | TXSTART;
432 writel(value, ®s->dma_opmode);
433
434 return 0;
435}
436
437static int xgmac_tx(struct eth_device *dev, volatile void *packet, int length)
438{
439 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
440 struct calxeda_eth_dev *priv = dev->priv;
441 u32 currdesc = priv->tx_currdesc;
442 struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
443 int timeout;
444
445 desc_set_buf_addr_and_size(txdesc, (void *)packet, length);
446 desc_set_tx_owner(txdesc, TXDESC_FIRST_SEG |
447 TXDESC_LAST_SEG | TXDESC_CRC_EN_APPEND);
448
449
450 writel(1, ®s->txpoll);
451
452 timeout = 1000000;
453 while (desc_get_owner(txdesc)) {
454 if (timeout-- < 0) {
455 printf("xgmac: TX timeout\n");
456 return -ETIMEDOUT;
457 }
458 udelay(1);
459 }
460
461 priv->tx_currdesc = (currdesc + 1) & (TX_NUM_DESC - 1);
462 return 0;
463}
464
465static int xgmac_rx(struct eth_device *dev)
466{
467 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
468 struct calxeda_eth_dev *priv = dev->priv;
469 u32 currdesc = priv->rx_currdesc;
470 struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
471 int length = 0;
472
473
474 if (desc_get_owner(rxdesc))
475 return -1;
476
477 length = desc_get_rx_frame_len(rxdesc);
478
479 NetReceive((volatile unsigned char *)desc_get_buf_addr(rxdesc), length);
480
481
482 desc_set_rx_owner(rxdesc);
483 writel(1, ®s->rxpoll);
484
485 priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
486
487 return length;
488}
489
490static void xgmac_halt(struct eth_device *dev)
491{
492 struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
493 struct calxeda_eth_dev *priv = dev->priv;
494 int value;
495
496
497 value = readl(®s->config);
498 value &= ~(RXENABLE | TXENABLE);
499 writel(value, ®s->config);
500
501
502 value = readl(®s->dma_opmode);
503 value &= ~(RXSTART | TXSTART);
504 writel(value, ®s->dma_opmode);
505
506
507 priv->tx_currdesc = 0;
508 priv->rx_currdesc = 0;
509}
510
511int calxedaxgmac_initialize(u32 id, ulong base_addr)
512{
513 struct eth_device *dev;
514 struct calxeda_eth_dev *priv;
515 struct xgmac_regs *regs;
516 u32 macaddr[2];
517
518 regs = (struct xgmac_regs *)base_addr;
519
520
521 if (readl(®s->version) != 0x1012)
522 return -1;
523
524 dev = malloc(sizeof(*dev));
525 if (!dev)
526 return 0;
527 memset(dev, 0, sizeof(*dev));
528
529
530 priv = memalign(32, sizeof(*priv));
531 if (!priv) {
532 free(dev);
533 return 0;
534 }
535
536 dev->iobase = (int)base_addr;
537 dev->priv = priv;
538 priv->dev = dev;
539 sprintf(dev->name, "xgmac%d", id);
540
541
542 macaddr[1] = readl(®s->macaddr[0].hi);
543 macaddr[0] = readl(®s->macaddr[0].lo);
544 memcpy(dev->enetaddr, macaddr, 6);
545
546 dev->init = xgmac_init;
547 dev->send = xgmac_tx;
548 dev->recv = xgmac_rx;
549 dev->halt = xgmac_halt;
550
551 eth_register(dev);
552
553 return 1;
554}
555
