1/* 2 * Copyright (C) 2005 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Embedded Planet EP88x boards. 6 * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26#ifndef __CONFIG_H 27#define __CONFIG_H 28 29#define CONFIG_MPC885 30 31#define CONFIG_EP88X /* Embedded Planet EP88x board */ 32 33#define CONFIG_SYS_TEXT_BASE 0xFC000000 34 35#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ 36 37/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ 38#define CONFIG_ENV_OVERWRITE 39 40#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 41#define CONFIG_BAUDRATE 38400 42 43#define CONFIG_ETHER_ON_FEC1 /* Enable Ethernet on FEC1 */ 44#define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ 45#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) 46#define CONFIG_SYS_DISCOVER_PHY 47#define CONFIG_MII_INIT 1 48#define FEC_ENET 49#endif /* CONFIG_FEC_ENET */ 50 51#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ 52#define CONFIG_8xx_CPUCLK_DEFAULT 100000000 53#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 54#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 55 56/* 57 * BOOTP options 58 */ 59#define CONFIG_BOOTP_BOOTFILESIZE 60#define CONFIG_BOOTP_BOOTPATH 61#define CONFIG_BOOTP_GATEWAY 62#define CONFIG_BOOTP_HOSTNAME 63 64 65/* 66 * Command line configuration. 67 */ 68#include <config_cmd_default.h> 69 70#define CONFIG_CMD_DHCP 71#define CONFIG_CMD_IMMAP 72#define CONFIG_CMD_MII 73#define CONFIG_CMD_PING 74 75 76#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ 77#define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ 78#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)" 79 80#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 81#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 82 83/*----------------------------------------------------------------------- 84 * Miscellaneous configurable options 85 */ 86#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 87#define CONFIG_SYS_HUSH_PARSER 88#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 89#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 90#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 91#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 92#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 93#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 94 95#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ 96 97#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 98 99#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 100 101/*----------------------------------------------------------------------- 102 * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) 103 */ 104#define CONFIG_SYS_SDRAM_BASE 0x00000000 105#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* Up to 128 Mbyte */ 106 107#define CONFIG_SYS_MAMR 0x00805000 108 109/* 110 * 4096 Up to 4096 SDRAM rows 111 * 1000 factor s -> ms 112 * 32 PTP (pre-divider from MPTPR) 113 * 4 Number of refresh cycles per period 114 * 64 Refresh cycle in ms per number of rows 115 */ 116#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 117 118#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 119#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ 120 121#define CONFIG_SYS_RESET_ADDRESS 0x09900000 122 123/*----------------------------------------------------------------------- 124 * For booting Linux, the board info and command line data 125 * have to be in the first 8 MB of memory, since this is 126 * the maximum mapped by the Linux kernel during initialization. 127 */ 128#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 129 130#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 131#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ 132#ifdef CONFIG_BZIP2 133#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve ~4 MB for malloc() */ 134#else 135#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 136#endif /* CONFIG_BZIP2 */ 137 138/*----------------------------------------------------------------------- 139 * Flash organisation 140 */ 141#define CONFIG_SYS_FLASH_BASE 0xFC000000 142#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 143#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 144#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 145#define CONFIG_SYS_MAX_FLASH_SECT 512 /* Max num of sects on one chip */ 146 147/* Environment is in flash */ 148#define CONFIG_ENV_IS_IN_FLASH 149#define CONFIG_ENV_SECT_SIZE 0x20000 /* We use one complete sector */ 150#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 151 152#define CONFIG_SYS_OR0_PRELIM 0xFC000160 153#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V) 154 155#define CONFIG_SYS_DIRECT_FLASH_TFTP 156 157/*----------------------------------------------------------------------- 158 * BCSR 159 */ 160#define CONFIG_SYS_OR3_PRELIM 0xFF0005B0 161#define CONFIG_SYS_BR3_PRELIM (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V) 162 163#define CONFIG_SYS_BCSR 0xFA400000 164 165/*----------------------------------------------------------------------- 166 * Internal Memory Map Register 167 */ 168#define CONFIG_SYS_IMMR 0xF0000000 169 170/*----------------------------------------------------------------------- 171 * Definitions for initial stack pointer and data area (in DPRAM) 172 */ 173#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 174#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 176#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 177 178/*----------------------------------------------------------------------- 179 * Configuration registers 180 */ 181#ifdef CONFIG_WATCHDOG 182#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 183 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ 184 SYPCR_SWP) 185#else 186#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 187 SYPCR_SWF | SYPCR_SWP) 188#endif /* CONFIG_WATCHDOG */ 189 190#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) 191 192/* TBSCR - Time Base Status and Control Register */ 193#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) 194 195/* PISCR - Periodic Interrupt Status and Control */ 196#define CONFIG_SYS_PISCR PISCR_PS 197 198/* SCCR - System Clock and reset Control Register */ 199#define SCCR_MASK SCCR_EBDF11 200#define CONFIG_SYS_SCCR SCCR_RTSEL 201 202#define CONFIG_SYS_DER 0 203 204/*----------------------------------------------------------------------- 205 * Cache Configuration 206 */ 207#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ 208 209#endif /* __CONFIG_H */ 210