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25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29
30#define CONFIG_BOOKE
31#define CONFIG_E500
32#define CONFIG_MPC85xx
33#define CONFIG_FSL_ELBC
34#define CONFIG_FSL_LAW
35#define CONFIG_P2020
36#define CONFIG_HWW1U1A
37#define CONFIG_MP
38#define CONFIG_HWCONFIG
39
40#define CONFIG_L2_CACHE
41#define CONFIG_BTB
42
43#define CONFIG_PANIC_HANG
44#define CONFIG_BOARD_EARLY_INIT_R
45#define CONFIG_CMD_REGINFO
46
47
48
49
50
51#define CONFIG_ENABLE_36BIT_PHYS
52#define CONFIG_PHYS_64BIT
53#define CONFIG_ADDR_MAP
54#define CONFIG_SYS_NUM_ADDR_MAP 16
55
56
57#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
58
59
60#define CONFIG_SYS_INIT_RAM_LOCK
61#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
62
63
64#define CONFIG_SYS_GBL_DATA_OFFSET \
65 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
66
67
68#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
69
70
71#define CONFIG_CMD_IRQ
72#define CONFIG_SYS_HZ 1000
73
74
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80
81
82
83#define CONFIG_SYS_CLK_FREQ 66666000
84#define CONFIG_DDR_CLK_FREQ 66666000
85
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101
102
103
104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
105#define CONFIG_SYS_SDRAM_BASE 0x00000000
106#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
107#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
108#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
109#define CONFIG_SYS_FLASH_BASE 0xe0000000
110#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
111#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
112#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
113#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
114#define CONFIG_SYS_CCSRBAR 0xffe00000
115
116#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000
117#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
118#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
119#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000
120#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
121#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
122
123
124#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
125#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
126#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
127#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
128#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
129#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
130#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
131#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
132#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
133#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xffd00000
134#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
135#define CONFIG_SYS_CCSRBAR_PHYS_LOW 0xffe00000
136
137
138
139
140
141#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
142#define CONFIG_SYS_TEXT_BASE 0xeff80000
143#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
144#define CONFIG_SYS_MONITOR_LEN 0x80000
145
146
147
148
149
150#define CONFIG_ENV_IS_IN_FLASH
151#define CONFIG_ENV_OVERWRITE
152#define CONFIG_ENV_SECT_SIZE 0x20000
153#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
154#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
155
156
157#define CONFIG_ENV_SIZE 0x2000
158#define CONFIG_ENV_SIZE_REDUND 0x2000
159
160
161
162
163
164#define CONFIG_CONS_INDEX 1
165#define CONFIG_SYS_NS16550
166#define CONFIG_SYS_NS16550_SERIAL
167#define CONFIG_SYS_NS16550_REG_SIZE 1
168#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
169
170#define CONFIG_BAUDRATE 115200
171#define CONFIG_SYS_BAUDRATE_TABLE \
172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
173
174#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
175#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
176
177
178#define CONFIG_LOADS_ECHO
179
180
181#define CONFIG_SYS_LOADS_BAUD_CHANGE
182
183
184
185
186
187#define CONFIG_PCI
188#define CONFIG_PCI_PNP
189#define CONFIG_CMD_PCI
190#define CONFIG_FSL_PCI_INIT
191#define CONFIG_FSL_PCIE_RESET
192#define CONFIG_SYS_PCI_64BIT
193#define CONFIG_PCI_SCAN_SHOW
194
195
196#define CONFIG_PCIE3
197#undef CONFIG_PCIE2
198#define CONFIG_PCIE1
199
200
201#define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
202#define CONFIG_SYS_PCIE2_NAME "Unused"
203#define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
204
205
206
207
208
209#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
210#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
211#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
212#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
213#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
214#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
215
216
217
218
219
220#define CONFIG_HARD_I2C
221#define CONFIG_FSL_I2C
222#define CONFIG_CMD_I2C
223#define CONFIG_I2C_MULTI_BUS
224#define CONFIG_SYS_I2C_OFFSET 0x3000
225#define CONFIG_SYS_I2C2_OFFSET 0x3100
226
227
228#define CONFIG_SYS_I2C_SPEED 400000
229#define CONFIG_SYS_I2C_SLAVE 0x7F
230
231
232#define CONFIG_SYS_SPD_BUS_NUM 0
233#define SPD_EEPROM_ADDRESS 0x51
234
235
236#define CONFIG_CMD_DATE
237#define CONFIG_RTC_DS1337
238#define CONFIG_SYS_RTC_BUS_NUM 0
239#define CONFIG_SYS_I2C_RTC_ADDR 0x68
240
241#define CONFIG_SYS_RTC_DS1337_NOOSC
242
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251
252
253
254#define CONFIG_CMD_EEPROM
255#define CONFIG_ENV_EEPROM_IS_ON_I2C
256#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
257#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
258#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
259#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
260
261
262
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264
265
266#define CONFIG_PCA953X
267#define CONFIG_CMD_PCA953X
268#define CONFIG_CMD_PCA953X_INFO
269#define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
270
271
272
273
274
275#define CONFIG_FSL_DDR2
276#define CONFIG_DDR_ECC
277#define CONFIG_DDR_SPD
278#define CONFIG_SPD_EEPROM
279#define CONFIG_VERY_BIG_RAM
280#define CONFIG_CMD_SDRAM
281
282
283#define CONFIG_NUM_DDR_CONTROLLERS 1
284#define CONFIG_DIMM_SLOTS_PER_CTLR 1
285#define CONFIG_CHIP_SELECTS_PER_CTRL 2
286
287
288#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
289#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
290
291
292
293
294
295#define CONFIG_FLASH_CFI_DRIVER
296#define CONFIG_SYS_FLASH_CFI
297#define CONFIG_SYS_FLASH_EMPTY_INFO
298#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
299
300
301#define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
302#define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
303#define CONFIG_SYS_MAX_FLASH_BANKS 2
304#define CONFIG_SYS_MAX_FLASH_SECT 1024
305#define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
306
307
308
309
310
311
312
313#define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
314#define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
315 | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
316
317
318#define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
319#define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
320#define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
321#define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
322
323
324#define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL
325#define CONFIG_SYS_FLASH_WRITE_TOUT 500UL
326
327
328#define CONFIG_SYS_FLASH_QUIET_TEST
329
330
331#define CONFIG_FLASH_SHOW_PROGRESS 45
332
333
334
335
336
337#define CONFIG_MII
338#define CONFIG_MII_DEFAULT_TSEC
339#define CONFIG_PHY_GIGE
340#define CONFIG_ETHPRIME "e1000#0"
341
342
343#define CONFIG_CMD_DHCP
344#define CONFIG_CMD_MII
345#define CONFIG_CMD_NET
346#define CONFIG_CMD_PING
347
348
349#define CONFIG_TSEC_ENET
350#define CONFIG_TSEC1
351#define CONFIG_TSEC2
352#define CONFIG_TSEC3
353#define CONFIG_TSEC1_NAME "owt0"
354#define CONFIG_TSEC2_NAME "owt1"
355#define CONFIG_TSEC3_NAME "peer"
356#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
357#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
358#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
359#define TSEC1_PHYIDX 0
360#define TSEC2_PHYIDX 0
361#define TSEC3_PHYIDX 0
362#define TSEC1_PHY_ADDR 2
363#define TSEC2_PHY_ADDR 3
364#define TSEC3_PHY_ADDR 4
365#define TSEC3_PHY_ADDR_CPUA 4
366#define TSEC3_PHY_ADDR_CPUB 5
367
368
369#define CONFIG_E1000
370#define CONFIG_E1000_SPI
371#define CONFIG_E1000_SPI_GENERIC
372#define CONFIG_CMD_E1000
373
374
375#define CONFIG_SPI
376#define CONFIG_SPI_X
377#define CONFIG_CMD_SPI
378#define MAX_SPI_BYTES 32
379
380
381
382
383
384#define CONFIG_USB_EHCI
385#define CONFIG_USB_EHCI_FSL
386#define CONFIG_USB_STORAGE
387#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
388#define CONFIG_CMD_USB
389
390
391#define CONFIG_DOS_PARTITION
392#define CONFIG_EFI_PARTITION
393#define CONFIG_ISO_PARTITION
394#define CONFIG_CMD_EXT2
395#define CONFIG_CMD_FAT
396
397
398
399
400
401#define CONFIG_CMDLINE_EDITING
402#define CONFIG_COMMAND_HISTORY
403#define CONFIG_AUTO_COMPLETE
404#define CONFIG_SYS_LONGHELP
405#define CONFIG_SYS_MAXARGS 128
406#define CONFIG_SYS_PBSIZE 8192
407#define CONFIG_SYS_CBSIZE 4096
408#define CONFIG_SYS_BARGSIZE 4096
409#define CONFIG_SYS_HUSH_PARSER
410#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
411
412
413#define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
414#ifndef __ASSEMBLY__
415const char *hww1u1a_get_ps1(void);
416#endif
417
418
419#include <config_cmd_default.h>
420
421
422#define CONFIG_MD5
423#define CONFIG_SHA1
424#define CONFIG_CMD_MD5SUM
425#define CONFIG_CMD_SHA1
426#define CONFIG_CMD_ASKENV
427#define CONFIG_CMD_SETEXPR
428
429
430
431
432
433
434
435#define CONFIG_OF_LIBFDT
436#define CONFIG_OF_BOARD_SETUP
437#define CONFIG_OF_STDOUT_VIA_ALIAS
438
439
440
441
442
443
444#define CONFIG_CMD_ELF
445#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
446#define CONFIG_SYS_BOOTM_LEN (64 << 20)
447
448
449#define CONFIG_LOADADDR 100000
450#define CONFIG_SYS_LOAD_ADDR 0x100000
451
452
453#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_LOAD_ADDR
454#define CONFIG_SYS_MEMTEST_END 0x7f000000
455
456#define CONFIG_BOOTDELAY 20
457#define CONFIG_BOOTCOMMAND "echo Not yet flashed"
458#define CONFIG_BOOTARGS ""
459#define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
460
461
462#define CONFIG_EXTRA_ENV_SETTINGS \
463 "ethprime=e1000#0\0" \
464 "ethrotate=no\0" \
465 "setbootargs=setenv bootargs " \
466 "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0" \
467 "perf_mode=performance\0" \
468 "hwconfig=" "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
469 "usb1:dr_mode=host,phy_type=ulpi\0" \
470 "flkernel=0xe8000000\0" \
471 "flinitramfs=0xe8800000\0" \
472 "fldevicetree=0xeff20000\0" \
473 "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0" \
474 "flboot=run preboot; run flbootm\0" \
475 "restore_eeprom=i2c dev 0 && " \
476 "eeprom read $loadaddr 0x0000 0x2000 && " \
477 "env import -c $loadaddr 0x2000\0"
478
479#endif
480