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23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26#include <version.h>
27
28
29
30
31#define CONFIG_E300 1
32#define CONFIG_MPC83xx 1
33#define CONFIG_MPC837x 1
34#define CONFIG_MPC8377 1
35
36#define CONFIG_SYS_TEXT_BASE 0xFC000000
37
38#define CONFIG_PCI 1
39
40#define CONFIG_MASK_AER_AO
41#define CONFIG_DISPLAY_AER_FULL
42
43#define CONFIG_MISC_INIT_R
44
45
46
47
48#define CONFIG_TSEC_ENET
49
50
51
52
53#define CONFIG_83XX_CLKIN 66666667
54#define CONFIG_PCIE
55#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
56#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
57
58
59
60
61#define CONFIG_SYS_HRCW_LOW 0
62#define CONFIG_SYS_HRCW_HIGH 0
63
64
65#define CONFIG_SYS_ACR_PIPE_DEP 3
66#define CONFIG_SYS_ACR_RPTCNT 3
67
68
69#define CONFIG_SYS_SPCR_TSECEP 3
70
71
72#define CONFIG_SYS_SCCR_TSEC1CM 3
73#define CONFIG_SYS_SCCR_TSEC2CM 0
74#define CONFIG_SYS_SCCR_SDHCCM 3
75#define CONFIG_SYS_SCCR_ENCCM 3
76#define CONFIG_SYS_SCCR_USBDRCM CONFIG_SYS_SCCR_ENCCM
77#define CONFIG_SYS_SCCR_PCIEXP1CM 3
78#define CONFIG_SYS_SCCR_PCIEXP2CM 3
79#define CONFIG_SYS_SCCR_PCICM 1
80#define CONFIG_SYS_SCCR_SATACM 0xFF
81
82
83
84
85#define CONFIG_SYS_SICRH 0x087c0000
86#define CONFIG_SYS_SICRL 0x40000000
87
88
89
90
91#define CONFIG_SYS_OBIR 0x30000000
92
93
94
95
96#define CONFIG_SYS_IMMR 0xE0000000
97
98
99
100
101#define CONFIG_SYS_DDR_BASE 0x00000000
102#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
103#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
104#define CONFIG_SYS_83XX_DDR_USES_CS0
105
106#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN | DDRCDR_PZ_HIZ |\
107 DDRCDR_NZ_HIZ | DDRCDR_ODT |\
108 DDRCDR_Q_DRN)
109
110#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
111
112#define CONFIG_SYS_DDR_MODE_WEAK
113#define CONFIG_SYS_DDR_WRITE_DATA_DELAY 2
114#define CONFIG_SYS_DDR_CPO 0x1f
115
116
117
118
119#define CONFIG_SPD_EEPROM
120#define SPD_EEPROM_ADDRESS 0x50
121#define SPD_EEPROM_OFFSET 0x20
122#define SPD_EEPROM_ADDR_LEN 2
123
124
125
126
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
128#define CONFIG_SYS_MONITOR_LEN (512*1024)
129#define CONFIG_SYS_MALLOC_LEN (512*1024)
130
131
132
133
134#define CONFIG_SYS_INIT_RAM_LOCK 1
135#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
136#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
137#define CONFIG_SYS_GBL_DATA_SIZE 0x100
138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
139 CONFIG_SYS_GBL_DATA_SIZE)
140
141
142
143
144#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
145#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
146#define CONFIG_SYS_LBC_LBCR 0x00000000
147#define CONFIG_FSL_ELBC 1
148
149
150
151
152#define CONFIG_SYS_FLASH_CFI
153#define CONFIG_FLASH_CFI_DRIVER
154#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
155
156#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
157#define CONFIG_SYS_FLASH_SIZE 64
158
159#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
160#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
161
162#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
163 BR_MS_GPCM | BR_V)
164#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
165 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
166 OR_GPCM_XACS | OR_GPCM_SCY_15 |\
167 OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
168 OR_GPCM_EAD)
169
170#define CONFIG_SYS_MAX_FLASH_BANKS 1
171#define CONFIG_SYS_MAX_FLASH_SECT 512
172
173#undef CONFIG_SYS_FLASH_CHECKSUM
174#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
175#define CONFIG_SYS_FLASH_WRITE_TOUT 500
176
177
178
179
180#define CONFIG_MTD_NAND_VERIFY_WRITE 1
181#define CONFIG_SYS_MAX_NAND_DEVICE 1
182#define CONFIG_NAND_FSL_ELBC 1
183
184#define CONFIG_SYS_NAND_BASE 0xE0600000
185#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
186 BR_PS_8 | BR_MS_FCM | BR_V)
187#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
188 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
189 OR_FCM_TRLX | OR_FCM_EHTR)
190
191#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
192#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
193
194
195
196
197#define CONFIG_CONS_INDEX 1
198#define CONFIG_SYS_NS16550
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
202
203#define CONFIG_SYS_BAUDRATE_TABLE \
204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
205
206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
208
209#define CONFIG_CONSOLE ttyS0
210#define CONFIG_BAUDRATE 115200
211
212
213#define CONFIG_FSL_SERDES
214#define CONFIG_FSL_SERDES1 0xe3000
215#define CONFIG_FSL_SERDES2 0xe3100
216
217
218#define CONFIG_SYS_HUSH_PARSER
219#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
220
221
222#define CONFIG_OF_LIBFDT 1
223#define CONFIG_OF_BOARD_SETUP 1
224#define CONFIG_OF_STDOUT_VIA_ALIAS 1
225
226
227#define CONFIG_HARD_I2C
228#define CONFIG_FSL_I2C
229#define CONFIG_I2C_MULTI_BUS
230#define CONFIG_SYS_I2C_SPEED 120000
231#define CONFIG_SYS_I2C_SLAVE 0x7F
232#define CONFIG_SYS_I2C_OFFSET 0x3000
233#define CONFIG_SYS_I2C2_OFFSET 0x3100
234
235
236
237
238
239#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
240#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
241#define CONFIG_SYS_PCI_MEM_SIZE (256 << 20)
242#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
243#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
244#define CONFIG_SYS_PCI_MMIO_SIZE (256 << 20)
245#define CONFIG_SYS_PCI_IO_BASE 0x00000000
246#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
247#define CONFIG_SYS_PCI_IO_SIZE (1 << 20)
248
249#ifdef CONFIG_PCIE
250#define CONFIG_SYS_PCIE1_BASE 0xA0000000
251#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
252#define CONFIG_SYS_PCIE1_CFG_SIZE (128 << 20)
253#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
254#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
255#define CONFIG_SYS_PCIE1_MEM_SIZE (256 << 20)
256#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
257#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
258#define CONFIG_SYS_PCIE1_IO_SIZE (8 << 20)
259
260#define CONFIG_SYS_PCIE2_BASE 0xC0000000
261#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
262#define CONFIG_SYS_PCIE2_CFG_SIZE (128 << 20)
263#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
264#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
265#define CONFIG_SYS_PCIE2_MEM_SIZE (256 << 20)
266#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
267#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
268#define CONFIG_SYS_PCIE2_IO_SIZE (8 << 20)
269#endif
270
271#define CONFIG_PCI_PNP
272#define CONFIG_PCI_SCAN_SHOW
273#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
274
275
276
277
278#define CONFIG_GMII
279#define CONFIG_SYS_VSC8601_SKEWFIX
280#define CONFIG_SYS_VSC8601_SKEW_TX 3
281#define CONFIG_SYS_VSC8601_SKEW_RX 3
282
283#define CONFIG_TSEC1
284#define CONFIG_HAS_ETH0
285#define CONFIG_TSEC1_NAME "TSEC0"
286#define CONFIG_SYS_TSEC1_OFFSET 0x24000
287#define TSEC1_PHY_ADDR 0x10
288#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
289#define TSEC1_PHYIDX 0
290
291#define CONFIG_ETHPRIME "TSEC0"
292#define CONFIG_HAS_ETH0
293
294
295
296
297#define CONFIG_LIBATA
298#define CONFIG_FSL_SATA
299
300#define CONFIG_SYS_SATA_MAX_DEVICE 2
301#define CONFIG_SATA1
302#define CONFIG_SYS_SATA1_OFFSET 0x18000
303#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
304#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
305#define CONFIG_SATA2
306#define CONFIG_SYS_SATA2_OFFSET 0x19000
307#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
308#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
309
310#define CONFIG_LBA48
311#define CONFIG_CMD_SATA
312#define CONFIG_DOS_PARTITION
313#define CONFIG_CMD_EXT2
314
315
316
317
318#define CONFIG_BOOTP_BOOTFILESIZE
319#define CONFIG_BOOTP_BOOTPATH
320#define CONFIG_BOOTP_GATEWAY
321#define CONFIG_BOOTP_HOSTNAME
322#define CONFIG_BOOTP_VENDOREX
323#define CONFIG_BOOTP_SUBNETMASK
324#define CONFIG_BOOTP_DNS
325#define CONFIG_BOOTP_DNS2
326#define CONFIG_BOOTP_NTPSERVER
327#define CONFIG_BOOTP_RANDOM_DELAY
328#define CONFIG_BOOTP_SEND_HOSTNAME
329
330
331
332
333#include <config_cmd_default.h>
334
335#define CONFIG_CMD_ASKENV
336#define CONFIG_CMD_NAND
337#define CONFIG_CMD_PING
338#define CONFIG_CMD_EEPROM
339#define CONFIG_CMD_I2C
340#define CONFIG_CMD_MII
341#define CONFIG_CMD_PCI
342#define CONFIG_CMD_USB
343#define CONFIG_CMD_SPI
344#define CONFIG_CMD_DHCP
345#define CONFIG_CMD_UBI
346#define CONFIG_CMD_UBIFS
347#define CONFIG_CMD_MTDPARTS
348#define CONFIG_CMD_SATA
349
350#define CONFIG_CMD_EXT2
351#define CONFIG_CMD_FAT
352#define CONFIG_CMD_JFFS2
353
354#define CONFIG_RBTREE
355#define CONFIG_LZO
356
357#define CONFIG_MTD_DEVICE
358#define CONFIG_MTD_PARTITIONS
359
360#define CONFIG_FLASH_CFI_MTD
361#define MTDIDS_DEFAULT "nor0=NOR,nand0=NAND"
362#define MTDPARTS_DEFAULT "mtdparts=NOR:1M(u-boot),2M(FPGA);NAND:-(root)"
363
364#define CONFIG_FIT
365#define CONFIG_FIT_VERBOSE 1
366
367#define CONFIG_CMDLINE_EDITING 1
368#define CONFIG_AUTO_COMPLETE
369
370
371
372
373#define CONFIG_SYS_LONGHELP
374#define CONFIG_SYS_LOAD_ADDR 0x2000000
375#define CONFIG_LOADADDR 0x4000000
376#define CONFIG_SYS_PROMPT "=> "
377#define CONFIG_SYS_CBSIZE 256
378
379#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
380#define CONFIG_SYS_MAXARGS 16
381#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
382#define CONFIG_SYS_HZ 1000
383
384#define CONFIG_LOADS_ECHO 1
385#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
386
387#define CONFIG_SYS_MEMTEST_START (60<<20)
388#define CONFIG_SYS_MEMTEST_END (70<<20)
389
390
391
392
393
394
395#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
396
397
398
399
400#define CONFIG_SYS_HID0_INIT 0x000000000
401#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
402 HID0_ENABLE_INSTRUCTION_CACHE)
403#define CONFIG_SYS_HID2 HID2_HBE
404
405
406
407
408#define CONFIG_HIGH_BATS 1
409
410
411#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE
412
413#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\
414 BATL_MEMCOHERENCE)
415#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
416 BATU_VP)
417#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
418#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
419
420
421#define CONFIG_SYS_IBAT1L (0)
422#define CONFIG_SYS_IBAT1U (0)
423#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
424#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
425
426
427#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\
428 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
429#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
430 BATU_VP)
431#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
432#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
433
434
435#define CONFIG_SYS_IBAT3L (0)
436#define CONFIG_SYS_IBAT3U (0)
437#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
438#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
439
440
441#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
442 BATL_MEMCOHERENCE)
443#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
444 BATU_VS | BATU_VP)
445#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
446 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
447#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
448
449
450#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
451#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
452 BATU_VS | BATU_VP)
453#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
454#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
455
456
457#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
458 BATL_MEMCOHERENCE)
459#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
460 BATU_VS | BATU_VP)
461#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
462#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
463
464
465#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
466 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
467#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
468 BATU_VS | BATU_VP)
469#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
470#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
471
472
473
474
475#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
476#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
477#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
478#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
479#define CONFIG_SYS_EEPROM_SIZE 0x4000
480
481
482
483
484#define CONFIG_SYS_FLASH_PROTECTION
485#define CONFIG_ENV_OVERWRITE
486#define CONFIG_ENV_IS_IN_FLASH 1
487#define CONFIG_ENV_ADDR 0xFFD00000
488#define CONFIG_ENV_SECT_SIZE 0x20000
489#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
490
491
492
493
494#define CONFIG_VIDEO
495#define CONFIG_VIDEO_SM501_PCI
496#define VIDEO_FB_LITTLE_ENDIAN
497#define CONFIG_CMD_BMP
498#define CONFIG_VIDEO_SM501
499#define CONFIG_VIDEO_SM501_32BPP
500#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
501#define CONFIG_CFB_CONSOLE
502#define CONFIG_VIDEO_LOGO
503#define CONFIG_VIDEO_BMP_LOGO
504#define CONFIG_VGA_AS_SINGLE_DEVICE
505#define CONFIG_SPLASH_SCREEN
506#define CONFIG_SYS_CONSOLE_IS_IN_ENV
507#define CONFIG_VIDEO_BMP_GZIP
508#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
509
510
511
512
513#define CONFIG_MPC8XXX_SPI
514
515
516
517
518#define CONFIG_SYS_USB_HOST
519#define CONFIG_USB_EHCI
520#define CONFIG_USB_EHCI_FSL
521#define CONFIG_HAS_FSL_DR_USB
522#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
523
524#define CONFIG_USB_STORAGE
525#define CONFIG_USB_KEYBOARD
526
527
528
529#define CONFIG_BOOTDELAY 5
530#define CONFIG_AUTOBOOT_KEYED
531#define CONFIG_AUTOBOOT_STOP_STR "s"
532#define CONFIG_ZERO_BOOTDELAY_CHECK
533#define CONFIG_RESET_TO_RETRY 1000
534
535#define MV_CI "MergerBox"
536#define MV_VCI "MergerBox"
537#define MV_FPGA_DATA 0xfc100000
538#define MV_FPGA_SIZE 0x00200000
539
540#define CONFIG_SHOW_BOOT_PROGRESS 1
541
542#define MV_KERNEL_ADDR_RAM 0x02800000
543#define MV_DTB_ADDR_RAM 0x00600000
544#define MV_INITRD_ADDR_RAM 0x01000000
545#define MV_FITADDR 0xfc300000
546#define MV_SPLAH_ADDR 0xffe00000
547
548#define CONFIG_BOOTCOMMAND "run i2c_init;if test ${boot_sqfs} -eq 1;"\
549 "then; run fitboot;else;run ubiboot;fi;"
550#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
551
552#define XMK_STR(x) #x
553#define MK_STR(x) XMK_STR(x)
554
555#define CONFIG_EXTRA_ENV_SETTINGS \
556 "console_nr=0\0"\
557 "stdin=serial\0"\
558 "stdout=serial\0"\
559 "stderr=serial\0"\
560 "boot_sqfs=1\0"\
561 "usb_dr_mode=host\0"\
562 "bootfile=MergerBox.fit\0"\
563 "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\
564 "fpga=0\0"\
565 "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\
566 "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\
567 "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\
568 "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\
569 "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\
570 "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\
571 "fitaddr=" MK_STR(MV_FITADDR) "\0"\
572 "mv_version=" U_BOOT_VERSION "\0"\
573 "mtdids=" MTDIDS_DEFAULT "\0"\
574 "mtdparts=" MTDPARTS_DEFAULT "\0"\
575 "dhcp_client_id=" MV_CI "\0"\
576 "dhcp_vendor-class-identifier=" MV_VCI "\0"\
577 "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\
578 "protect off all;erase $uboota +0xC0000;"\
579 "cp.b $loadaddr $uboota $filesize\0"\
580 "upd_fpga=dhcp;tftp MergerBox.rbf;erase $fpgadata +$fpgadatasize;"\
581 "cp.b $loadaddr $fpgadata $filesize\0"\
582 "upd_fit=dhcp;tftp MergerBox.fit;erase $fitaddr +0x1000000;"\
583 "cp.b $loadaddr $fitaddr $filesize\0"\
584 "addsqshrfs=set bootargs $bootargs root=/dev/ram ro "\
585 "rootfstype=squashfs\0"\
586 "addubirfs=set bootargs $bootargs ubi.mtd=9 root=ubi0:rootfs rw "\
587 "rootfstype=ubifs\0"\
588 "addusbrfs=set bootargs $bootargs root=/dev/sda1 rw "\
589 "rootfstype=ext3 usb-storage.delay_use=1 rootdelay=3\0"\
590 "netusbboot=bootp;run fpganetload fitnetload addusbrfs doboot\0"\
591 "netubiboot= bootp;run fpganetload fitnetload addubirfs doboot\0"\
592 "ubiboot=run fitprep addubirfs;set mv_initrd_ram -;run doboot\0"\
593 "doboot=bootm $mv_kernel_ram $mv_initrd_ram $mv_dtb_ram\0"\
594 "fitprep=imxtract $fitaddr kernel $mv_kernel_ram;"\
595 "imxtract $fitaddr ramdisk $mv_initrd_ram;"\
596 "imxtract $fitaddr fdt $mv_dtb_ram\0"\
597 "fdtprep=fdt addr $mv_dtb_ram;fdt boardsetup\0"\
598 "fitboot=run fitprep fdtprep addsqshrfs doboot\0"\
599 "i2c_init=run i2c_speed init_sdi_tx i2c_init_pll\0"\
600 "i2c_init_pll=i2c mw 65 9 2;i2c mw 65 9 0;i2c mw 65 5 2b;"\
601 "i2c mw 65 7 f;i2c mw 65 8 f;i2c mw 65 11 40;i2c mw 65 12 40;"\
602 "i2c mw 65 13 40; i2c mw 65 14 40; i2c mw 65 a 0\0"\
603 "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
604 "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
605 "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
606 "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\
607 ""
608
609#undef MK_STR
610#undef XMK_STR
611
612
613
614
615#define CONFIG_FPGA_COUNT 1
616#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
617#define CONFIG_FPGA_ALTERA
618#define CONFIG_FPGA_CYCLON2
619
620#endif
621