1/* 2 * (C) Copyright 2001 3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#ifndef __ASSEMBLY__ 32#include <galileo/core.h> 33#endif 34 35#include "../board/evb64260/local.h" 36 37/* 38 * High Level Configuration Options 39 * (easy to change) 40 */ 41 42#define CONFIG_P3G4 1 /* this is a P3G4 board */ 43#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ 44 45#define CONFIG_SYS_TEXT_BASE 0xfff00000 46 47#define CONFIG_BAUDRATE 115200 /* console baudrate = 115200 */ 48 49#undef CONFIG_ECC /* enable ECC support */ 50/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */ 51 52/* which initialization functions to call for this board */ 53#define CONFIG_MISC_INIT_R 1 54#define CONFIG_BOARD_EARLY_INIT_F 1 55 56#define CONFIG_SYS_BOARD_NAME "P3G4" 57 58#undef CONFIG_SYS_HUSH_PARSER 59#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 60 61/* 62 * The following defines let you select what serial you want to use 63 * for your console driver. 64 * 65 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another 66 * mpsc channel, change CONFIG_MPSC_PORT to the desired value. 67 */ 68#define CONFIG_MPSC 69#define CONFIG_MPSC_PORT 0 70 71 72/* define this if you want to enable GT MAC filtering */ 73#define CONFIG_GT_USE_MAC_HASH_TABLE 74 75#undef CONFIG_ETHER_PORT_MII /* use RMII */ 76 77#if 0 78#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 79#else 80#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 81#endif 82#define CONFIG_ZERO_BOOTDELAY_CHECK 83 84#define CONFIG_PREBOOT "echo;" \ 85 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 86 "echo" 87 88#undef CONFIG_BOOTARGS 89 90#define CONFIG_EXTRA_ENV_SETTINGS \ 91 "netdev=eth0\0" \ 92 "hostname=p3g4\0" \ 93 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 94 "nfsroot=${serverip}:${rootpath}\0" \ 95 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 96 "addip=setenv bootargs ${bootargs} " \ 97 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 98 ":${hostname}:${netdev}:off panic=1\0" \ 99 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 100 "flash_nfs=run nfsargs addip addtty;" \ 101 "bootm ${kernel_addr}\0" \ 102 "flash_self=run ramargs addip addtty;" \ 103 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 104 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 105 "bootm\0" \ 106 "rootpath=/opt/eldk/ppc_74xx\0" \ 107 "bootfile=/tftpboot/p3g4/uImage\0" \ 108 "kernel_addr=ff000000\0" \ 109 "ramdisk_addr=ff010000\0" \ 110 "load=tftp 100000 /tftpboot/p3g4/u-boot.bin\0" \ 111 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ 112 "cp.b 100000 fff00000 ${filesize};" \ 113 "setenv filesize;saveenv\0" \ 114 "upd=run load update\0" \ 115 "" 116#define CONFIG_BOOTCOMMAND "run flash_self" 117 118#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 119#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 120 121#undef CONFIG_WATCHDOG /* watchdog disabled */ 122#undef CONFIG_ALTIVEC /* undef to disable */ 123 124/* 125 * BOOTP options 126 */ 127#define CONFIG_BOOTP_SUBNETMASK 128#define CONFIG_BOOTP_GATEWAY 129#define CONFIG_BOOTP_HOSTNAME 130#define CONFIG_BOOTP_BOOTPATH 131#define CONFIG_BOOTP_BOOTFILESIZE 132 133 134#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 135 136 137/* 138 * Command line configuration. 139 */ 140#include <config_cmd_default.h> 141 142#define CONFIG_CMD_ASKENV 143#define CONFIG_CMD_DHCP 144#define CONFIG_CMD_PCI 145#define CONFIG_CMD_ELF 146#define CONFIG_CMD_MII 147#define CONFIG_CMD_PING 148#define CONFIG_CMD_UNIVERSE 149#define CONFIG_CMD_BSP 150 151 152/* 153 * Miscellaneous configurable options 154 */ 155#define CONFIG_SYS_LONGHELP /* undef to save memory */ 156#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 157#if defined(CONFIG_CMD_KGDB) 158#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 159#else 160#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 161#endif 162#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 163#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 164#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 165 166#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 167#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ 168 169#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ 170 171#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 172#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ 173 174#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 175 176 177/* 178 * Low Level Configuration Settings 179 * (address mappings, register initial values, etc.) 180 * You should know what you are doing if you make changes here. 181 */ 182 183/*----------------------------------------------------------------------- 184 * Definitions for initial stack pointer and data area 185 */ 186#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 187#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 189#define CONFIG_SYS_INIT_RAM_LOCK 190 191 192/*----------------------------------------------------------------------- 193 * Start addresses for the final memory configuration 194 * (Set up by the startup code) 195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 196 */ 197#define CONFIG_SYS_SDRAM_BASE 0x00000000 198#define CONFIG_SYS_FLASH_BASE 0xff000000 199#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 200#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 201#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 202#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 203 204/* areas to map different things with the GT in physical space */ 205#define CONFIG_SYS_DRAM_BANKS 1 206#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ 207 208/* What to put in the bats. */ 209#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 210 211/* Peripheral Device section */ 212#define CONFIG_SYS_GT_REGS 0xf8000000 213#define CONFIG_SYS_DEV_BASE 0xff000000 214 215#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE 216#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) 217#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) 218#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) 219 220#define CONFIG_SYS_DEV0_SIZE _8M /* Flash bank */ 221#define CONFIG_SYS_DEV1_SIZE 0 /* unused */ 222#define CONFIG_SYS_DEV2_SIZE 0 /* unused */ 223#define CONFIG_SYS_DEV3_SIZE 0 /* unused */ 224 225#define CONFIG_SYS_16BIT_BOOT_PAR 0xc01b5e7c 226#define CONFIG_SYS_DEV0_PAR CONFIG_SYS_16BIT_BOOT_PAR 227 228#if 0 /* Wrong?? NTL */ 229#define CONFIG_SYS_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */ 230 /* DMAAck[1:0] GNT0[1:0] */ 231#else 232#define CONFIG_SYS_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */ 233 /* REQ0[1:0] GNT0[1:0] */ 234#endif 235#define CONFIG_SYS_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */ 236 /* DMAReq[4] DMAAck[4] WDNMI WDE */ 237#if 0 /* Wrong?? NTL */ 238#define CONFIG_SYS_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */ 239 /* DMAAck[1:0] GNT1[1:0] */ 240#else 241#define CONFIG_SYS_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */ 242 /* GPP[22] (RS232IntB or PCI1Int) */ 243 /* GPP[21] (RS323IntA) */ 244 /* BClkIn */ 245 /* REQ1[1:0] GNT1[1:0] */ 246#endif 247 248#if 0 /* Wrong?? NTL */ 249# define CONFIG_SYS_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */ 250 /* GPP[27:26] Int[1:0] */ 251#else 252# define CONFIG_SYS_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */ 253 /* GPP[29] (PCI1Int) */ 254 /* BClkOut0 */ 255 /* GPP[27] (PCI0Int) */ 256 /* GPP[26] (RtcInt or PCI1Int) */ 257 /* CPUInt[25:24] */ 258#endif 259 260#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001102 /* 11=MPSC1/MPSC0 02=ETH 0 and 2 RMII */ 261 262#if 0 /* Wrong?? - NTL */ 263# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x000002c6 264#else 265# define CONFIG_SYS_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */ 266 /* gpp[29] */ 267 /* gpp[27:26] */ 268 /* gpp[22:21] */ 269 270# define CONFIG_SYS_SDRAM_CONFIG 0xd8e18200 /* 0x448 */ 271 /* idmas use buffer 1,1 272 comm use buffer 0 273 pci use buffer 1,1 274 cpu use buffer 0 275 normal load (see also ifdef HVL) 276 standard SDRAM (see also ifdef REG) 277 non staggered refresh */ 278 /* 31:26 25 23 20 19 18 16 */ 279 /* 110110 00 111 0 0 00 1 */ 280 /* refresh_count=0x200 281 phisical interleaving disable 282 virtual interleaving enable */ 283 /* 15 14 13:0 */ 284 /* 1 0 0x200 */ 285#endif 286 287#if 0 288#define CONFIG_SYS_DUART_IO CONFIG_SYS_DEV2_SPACE 289#define CONFIG_SYS_DUART_CHAN 1 /* channel to use for console */ 290#endif 291#undef CONFIG_SYS_INIT_CHAN1 292#undef CONFIG_SYS_INIT_CHAN2 293#if 0 294#define SRAM_BASE CONFIG_SYS_DEV0_SPACE 295#define SRAM_SIZE 0x00100000 /* 1 MB of sram */ 296#endif 297 298 299/*----------------------------------------------------------------------- 300 * PCI stuff 301 *----------------------------------------------------------------------- 302 */ 303 304#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 305#define PCI_HOST_FORCE 1 /* configure as pci host */ 306#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 307 308#define CONFIG_PCI /* include pci support */ 309#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 310#define CONFIG_PCI_PNP /* do pci plug-and-play */ 311 312/* PCI MEMORY MAP section */ 313#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 314#define CONFIG_SYS_PCI0_MEM_SIZE _128M 315#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) 316 317#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 318#define CONFIG_SYS_PCI1_MEM_SIZE _128M 319#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) 320 321/* PCI I/O MAP section */ 322#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 323#define CONFIG_SYS_PCI0_IO_SIZE _16M 324#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) 325#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 326 327#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 328#define CONFIG_SYS_PCI1_IO_SIZE _16M 329#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) 330#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 331 332/*---------------------------------------------------------------------- 333 * Initial BAT mappings 334 */ 335 336/* NOTES: 337 * 1) GUARDED and WRITE_THRU not allowed in IBATS 338 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT 339 */ 340 341/* SDRAM */ 342#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 343#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 344#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 345#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 346 347/* init ram */ 348#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 349#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 350#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 351#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 352 353/* PCI0, PCI1 in one BAT */ 354#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS 355#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 356#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 357#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 358 359/* GT regs, bootrom, all the devices, PCI I/O */ 360#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) 361#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) 362#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 363#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 364 365/* I2C speed and slave address (for compatability) defaults */ 366#define CONFIG_SYS_I2C_SPEED 400000 367#define CONFIG_SYS_I2C_SLAVE 0x7F 368 369/* I2C addresses for the two DIMM SPD chips */ 370#ifndef CONFIG_EVB64260_750CX 371#define DIMM0_I2C_ADDR 0x56 372#define DIMM1_I2C_ADDR 0x54 373#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */ 374#define DIMM0_I2C_ADDR 0x54 375#define DIMM1_I2C_ADDR 0x54 376#endif 377 378/* 379 * For booting Linux, the board info and command line data 380 * have to be in the first 8 MB of memory, since this is 381 * the maximum mapped by the Linux kernel during initialization. 382 */ 383#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 384 385/*----------------------------------------------------------------------- 386 * FLASH organization 387 */ 388#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 389#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 390 391#define CONFIG_SYS_EXTRA_FLASH_DEVICE BOOT_DEVICE 392#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ 393#define CONFIG_SYS_BOOT_FLASH_WIDTH 2 /* 16 bit */ 394 395#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 396#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 397#define CONFIG_SYS_FLASH_CFI 1 398 399#define CONFIG_ENV_IS_IN_FLASH 1 400#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 401#define CONFIG_ENV_SECT_SIZE 0x20000 402#define CONFIG_ENV_ADDR 0xFFFE0000 403 404/*----------------------------------------------------------------------- 405 * Cache Configuration 406 */ 407#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 408#if defined(CONFIG_CMD_KGDB) 409#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 410#endif 411 412/*----------------------------------------------------------------------- 413 * L2CR setup -- make sure this is right for your board! 414 * look in include/74xx_7xx.h for the defines used here 415 */ 416 417#define CONFIG_SYS_L2 418 419#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 420 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 421 422#define L2_ENABLE (L2_INIT | L2CR_L2E) 423 424#define CONFIG_SYS_BOARD_ASM_INIT 1 425 426 427#endif /* __CONFIG_H */ 428