1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#undef CONFIG_SYS_RAMBOOT 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 39#define CONFIG_PM828 1 /* ...on a PM828 module */ 40#define CONFIG_CPM2 1 /* Has a CPM2 */ 41 42#ifndef CONFIG_SYS_TEXT_BASE 43#define CONFIG_SYS_TEXT_BASE 0x40000000 /* Standard: boot 64-bit flash */ 44#endif 45 46#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ 47 48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 49 50#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 51 52#undef CONFIG_BOOTARGS 53#define CONFIG_BOOTCOMMAND \ 54 "bootp;" \ 55 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 57 "bootm" 58 59/* enable I2C and select the hardware/software driver */ 60#undef CONFIG_HARD_I2C 61#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 62# define CONFIG_SYS_I2C_SPEED 50000 63# define CONFIG_SYS_I2C_SLAVE 0xFE 64/* 65 * Software (bit-bang) I2C driver configuration 66 */ 67#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 68#define I2C_ACTIVE (iop->pdir |= 0x00010000) 69#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 70#define I2C_READ ((iop->pdat & 0x00010000) != 0) 71#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 72 else iop->pdat &= ~0x00010000 73#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 74 else iop->pdat &= ~0x00020000 75#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 76 77 78#define CONFIG_RTC_PCF8563 79#define CONFIG_SYS_I2C_RTC_ADDR 0x51 80 81/* 82 * select serial console configuration 83 * 84 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 85 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 86 * for SCC). 87 * 88 * if CONFIG_CONS_NONE is defined, then the serial console routines must 89 * defined elsewhere (for example, on the cogent platform, there are serial 90 * ports on the motherboard which are used for the serial console - see 91 * cogent/cma101/serial.[ch]). 92 */ 93#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 94#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 95#undef CONFIG_CONS_NONE /* define if console on something else*/ 96#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 97 98/* 99 * select ethernet configuration 100 * 101 * if CONFIG_ETHER_ON_SCC is selected, then 102 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) 103 * 104 * if CONFIG_ETHER_ON_FCC is selected, then 105 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected 106 * 107 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 108 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 109 */ 110#undef CONFIG_ETHER_NONE /* define if ether on something else */ 111 112#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 113#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ 114 115#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 116/* 117 * - Rx-CLK is CLK11 118 * - Tx-CLK is CLK10 119 */ 120#define CONFIG_ETHER_ON_FCC1 121# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 122#ifndef CONFIG_DB_CR826_J30x_ON 123# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) 124#else 125# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) 126#endif 127/* 128 * - Rx-CLK is CLK15 129 * - Tx-CLK is CLK14 130 */ 131#define CONFIG_ETHER_ON_FCC2 132# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 133# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 134/* 135 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 136 * - Enable Full Duplex in FSMR 137 */ 138# define CONFIG_SYS_CPMFCR_RAMTYPE 0 139# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 140 141/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 142#define CONFIG_8260_CLKIN 100000000 /* in Hz */ 143 144#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 145#define CONFIG_BAUDRATE 230400 146#else 147#define CONFIG_BAUDRATE 9600 148#endif 149 150#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 151#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 152 153#undef CONFIG_WATCHDOG /* watchdog disabled */ 154 155/* 156 * BOOTP options 157 */ 158#define CONFIG_BOOTP_SUBNETMASK 159#define CONFIG_BOOTP_GATEWAY 160#define CONFIG_BOOTP_HOSTNAME 161#define CONFIG_BOOTP_BOOTPATH 162#define CONFIG_BOOTP_BOOTFILESIZE 163 164 165/* 166 * Command line configuration. 167 */ 168#include <config_cmd_default.h> 169 170#define CONFIG_CMD_BEDBUG 171#define CONFIG_CMD_DATE 172#define CONFIG_CMD_DHCP 173#define CONFIG_CMD_EEPROM 174#define CONFIG_CMD_I2C 175#define CONFIG_CMD_NFS 176#define CONFIG_CMD_SNTP 177 178#ifdef CONFIG_PCI 179#define CONFIG_CMD_PCI 180#endif 181 182/* 183 * Miscellaneous configurable options 184 */ 185#define CONFIG_SYS_LONGHELP /* undef to save memory */ 186#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 187#if defined(CONFIG_CMD_KGDB) 188#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 189#else 190#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 191#endif 192#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 193#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 194#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 195 196#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 197#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 198 199#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 200 201#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 202 203#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 204 205#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 206 207/* 208 * For booting Linux, the board info and command line data 209 * have to be in the first 8 MB of memory, since this is 210 * the maximum mapped by the Linux kernel during initialization. 211 */ 212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 213 214/*----------------------------------------------------------------------- 215 * Flash and Boot ROM mapping 216 */ 217 218#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 219#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 220#define CONFIG_SYS_FLASH0_BASE 0x40000000 221#define CONFIG_SYS_FLASH0_SIZE 0x02000000 222#define CONFIG_SYS_DOC_BASE 0xFF800000 223#define CONFIG_SYS_DOC_SIZE 0x00100000 224 225 226/* Flash bank size (for preliminary settings) 227 */ 228#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 229 230/*----------------------------------------------------------------------- 231 * FLASH organization 232 */ 233#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 234#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ 235 236#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 237#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 238 239#if 0 240/* Start port with environment in flash; switch to EEPROM later */ 241#define CONFIG_ENV_IS_IN_FLASH 1 242#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) 243#define CONFIG_ENV_SIZE 0x40000 244#define CONFIG_ENV_SECT_SIZE 0x40000 245#else 246/* Final version: environment in EEPROM */ 247#define CONFIG_ENV_IS_IN_EEPROM 1 248#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 249#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 250#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 251#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 252#define CONFIG_ENV_OFFSET 512 253#define CONFIG_ENV_SIZE (2048 - 512) 254#endif 255 256/*----------------------------------------------------------------------- 257 * Hard Reset Configuration Words 258 * 259 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 260 * defines for the various registers affected by the HRCW e.g. changing 261 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 262 */ 263#if defined(CONFIG_BOOT_ROM) 264#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 265#else 266#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 267#endif 268 269/* no slaves so just fill with zeros */ 270#define CONFIG_SYS_HRCW_SLAVE1 0 271#define CONFIG_SYS_HRCW_SLAVE2 0 272#define CONFIG_SYS_HRCW_SLAVE3 0 273#define CONFIG_SYS_HRCW_SLAVE4 0 274#define CONFIG_SYS_HRCW_SLAVE5 0 275#define CONFIG_SYS_HRCW_SLAVE6 0 276#define CONFIG_SYS_HRCW_SLAVE7 0 277 278/*----------------------------------------------------------------------- 279 * Internal Memory Mapped Register 280 */ 281#define CONFIG_SYS_IMMR 0xF0000000 282 283/*----------------------------------------------------------------------- 284 * Definitions for initial stack pointer and data area (in DPRAM) 285 */ 286#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 287#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 288#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 289#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 290 291/*----------------------------------------------------------------------- 292 * Start addresses for the final memory configuration 293 * (Set up by the startup code) 294 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 295 * 296 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 297 * is mapped at SDRAM_BASE2_PRELIM. 298 */ 299#define CONFIG_SYS_SDRAM_BASE 0x00000000 300#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 301#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 302#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 303#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 304 305#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 306# define CONFIG_SYS_RAMBOOT 307#endif 308 309#ifdef CONFIG_PCI 310#define CONFIG_PCI_PNP 311#define CONFIG_EEPRO100 312#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 313#endif 314 315/*----------------------------------------------------------------------- 316 * Cache Configuration 317 */ 318#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 319#if defined(CONFIG_CMD_KGDB) 320# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 321#endif 322 323/*----------------------------------------------------------------------- 324 * HIDx - Hardware Implementation-dependent Registers 2-11 325 *----------------------------------------------------------------------- 326 * HID0 also contains cache control - initially enable both caches and 327 * invalidate contents, then the final state leaves only the instruction 328 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 329 * but Soft reset does not. 330 * 331 * HID1 has only read-only information - nothing to set. 332 */ 333#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 334 HID0_IFEM|HID0_ABE) 335#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 336#define CONFIG_SYS_HID2 0 337 338/*----------------------------------------------------------------------- 339 * RMR - Reset Mode Register 5-5 340 *----------------------------------------------------------------------- 341 * turn on Checkstop Reset Enable 342 */ 343#define CONFIG_SYS_RMR RMR_CSRE 344 345/*----------------------------------------------------------------------- 346 * BCR - Bus Configuration 4-25 347 *----------------------------------------------------------------------- 348 */ 349 350#define BCR_APD01 0x10000000 351#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 352 353/*----------------------------------------------------------------------- 354 * SIUMCR - SIU Module Configuration 4-31 355 *----------------------------------------------------------------------- 356 */ 357#if 0 358#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) 359#else 360#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 361#endif 362 363 364/*----------------------------------------------------------------------- 365 * SYPCR - System Protection Control 4-35 366 * SYPCR can only be written once after reset! 367 *----------------------------------------------------------------------- 368 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 369 */ 370#if defined(CONFIG_WATCHDOG) 371#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 372 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 373#else 374#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 375 SYPCR_SWRI|SYPCR_SWP) 376#endif /* CONFIG_WATCHDOG */ 377 378/*----------------------------------------------------------------------- 379 * TMCNTSC - Time Counter Status and Control 4-40 380 *----------------------------------------------------------------------- 381 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 382 * and enable Time Counter 383 */ 384#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 385 386/*----------------------------------------------------------------------- 387 * PISCR - Periodic Interrupt Status and Control 4-42 388 *----------------------------------------------------------------------- 389 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 390 * Periodic timer 391 */ 392#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 393 394/*----------------------------------------------------------------------- 395 * SCCR - System Clock Control 9-8 396 *----------------------------------------------------------------------- 397 */ 398#define CONFIG_SYS_SCCR (SCCR_DFBRG00) 399 400/*----------------------------------------------------------------------- 401 * RCCR - RISC Controller Configuration 13-7 402 *----------------------------------------------------------------------- 403 */ 404#define CONFIG_SYS_RCCR 0 405 406/* 407 * Init Memory Controller: 408 * 409 * Bank Bus Machine PortSz Device 410 * ---- --- ------- ------ ------ 411 * 0 60x GPCM 64 bit FLASH 412 * 1 60x SDRAM 64 bit SDRAM 413 * 414 */ 415 416 /* Initialize SDRAM on local bus 417 */ 418#define CONFIG_SYS_INIT_LOCAL_SDRAM 419 420 421/* Minimum mask to separate preliminary 422 * address ranges for CS[0:2] 423 */ 424#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 425 426/* 427 * we use the same values for 32 MB and 128 MB SDRAM 428 * refresh rate = 7.68 uS (100 MHz Bus Clock) 429 */ 430#define CONFIG_SYS_MPTPR 0x2000 431#define CONFIG_SYS_PSRT 0x16 432 433#define CONFIG_SYS_MRS_OFFS 0x00000000 434 435 436#if defined(CONFIG_BOOT_ROM) 437/* 438 * Bank 0 - Boot ROM (8 bit wide) 439 */ 440#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 441 BRx_PS_8 |\ 442 BRx_MS_GPCM_P |\ 443 BRx_V) 444 445#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 446 ORxG_CSNT |\ 447 ORxG_ACS_DIV1 |\ 448 ORxG_SCY_5_CLK |\ 449 ORxG_EHTR |\ 450 ORxG_TRLX) 451 452/* 453 * Bank 1 - Flash (64 bit wide) 454 */ 455#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 456 BRx_PS_64 |\ 457 BRx_MS_GPCM_P |\ 458 BRx_V) 459 460#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 461 ORxG_CSNT |\ 462 ORxG_ACS_DIV1 |\ 463 ORxG_SCY_5_CLK |\ 464 ORxG_EHTR |\ 465 ORxG_TRLX) 466 467#else /* ! CONFIG_BOOT_ROM */ 468 469/* 470 * Bank 0 - Flash (64 bit wide) 471 */ 472#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 473 BRx_PS_64 |\ 474 BRx_MS_GPCM_P |\ 475 BRx_V) 476 477#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 478 ORxG_CSNT |\ 479 ORxG_ACS_DIV1 |\ 480 ORxG_SCY_5_CLK |\ 481 ORxG_EHTR |\ 482 ORxG_TRLX) 483 484/* 485 * Bank 1 - Disk-On-Chip 486 */ 487#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ 488 BRx_PS_8 |\ 489 BRx_MS_GPCM_P |\ 490 BRx_V) 491 492#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ 493 ORxG_CSNT |\ 494 ORxG_ACS_DIV1 |\ 495 ORxG_SCY_5_CLK |\ 496 ORxG_EHTR |\ 497 ORxG_TRLX) 498 499#endif /* CONFIG_BOOT_ROM */ 500 501/* Bank 2 - SDRAM 502 */ 503 504#ifndef CONFIG_SYS_RAMBOOT 505#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 506 BRx_PS_64 |\ 507 BRx_MS_SDRAM_P |\ 508 BRx_V) 509 510 /* SDRAM initialization values for 8-column chips 511 */ 512#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ 513 ORxS_BPD_4 |\ 514 ORxS_ROWST_PBI0_A9 |\ 515 ORxS_NUMR_12) 516 517#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ 518 PSDMR_BSMA_A14_A16 |\ 519 PSDMR_SDA10_PBI0_A10 |\ 520 PSDMR_RFRC_7_CLK |\ 521 PSDMR_PRETOACT_2W |\ 522 PSDMR_ACTTORW_2W |\ 523 PSDMR_LDOTOPRE_1C |\ 524 PSDMR_WRC_1C |\ 525 PSDMR_CL_2) 526 527 /* SDRAM initialization values for 9-column chips 528 */ 529#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ 530 ORxS_BPD_4 |\ 531 ORxS_ROWST_PBI0_A7 |\ 532 ORxS_NUMR_13) 533 534#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ 535 PSDMR_BSMA_A13_A15 |\ 536 PSDMR_SDA10_PBI0_A9 |\ 537 PSDMR_RFRC_7_CLK |\ 538 PSDMR_PRETOACT_2W |\ 539 PSDMR_ACTTORW_2W |\ 540 PSDMR_LDOTOPRE_1C |\ 541 PSDMR_WRC_1C |\ 542 PSDMR_CL_2) 543 544#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL 545#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL 546 547#endif /* CONFIG_SYS_RAMBOOT */ 548 549#endif /* __CONFIG_H */ 550