1/* 2 * (C) Copyright 2001 3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#define CONFIG_SYS_GT_6426x GT_64260 /* with a 64260 system controller */ 32#define CONFIG_ETHER_PORT_MII /* use two MII ports */ 33#define CONFIG_INTEL_LXT97X /* Intel LXT97X phy */ 34 35#ifndef __ASSEMBLY__ 36#include <galileo/core.h> 37#endif 38 39#include "../board/evb64260/local.h" 40 41#define CONFIG_EVB64260 1 /* this is an EVB64260 board */ 42#define CONFIG_ZUMA_V2 1 /* always define this for ZUMA v2 */ 43 44#define CONFIG_SYS_TEXT_BASE 0xfff00000 45 46/* #define CONFIG_ZUMA_V2_OLD 1 */ /* backwards compat for old V2 board */ 47 48#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */ 49 50#define CONFIG_ECC /* enable ECC support */ 51 52#define CONFIG_750CX /* we have a 750CX/CXe (override local.h) */ 53 54/* which initialization functions to call for this board */ 55#define CONFIG_MISC_INIT_R 56#define CONFIG_BOARD_EARLY_INIT_F 57#define CONFIG_SYS_BOARD_ASM_INIT 58 59#define CONFIG_SYS_BOARD_NAME "Zuma APv2" 60 61#define CONFIG_SYS_HUSH_PARSER 62#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 63 64/* 65 * The following defines let you select what serial you want to use 66 * for your console driver. 67 * 68 * what to do: 69 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial 70 * cable onto the second DUART channel, change the CONFIG_SYS_DUART port from 1 71 * to 0 below. 72 * 73 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another 74 * mpsc channel, change CONFIG_MPSC_PORT to the desired value. 75 */ 76#define CONFIG_MPSC 77 78#define CONFIG_MPSC_PORT 0 79 80 81/* define this if you want to enable GT MAC filtering */ 82#define CONFIG_GT_USE_MAC_HASH_TABLE 83 84#if 1 85#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 86#else 87#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 88#endif 89#define CONFIG_ZERO_BOOTDELAY_CHECK 90 91#undef CONFIG_BOOTARGS 92 93#define CONFIG_BOOTCOMMAND \ 94 "tftpboot && " \ 95 "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \ 96 "ip=$ipaddr:$serverip:$gatewayip:" \ 97 "$netmask:$hostname:eth0:none panic=5 && bootm" 98 99#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ 100#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */ 101 102#undef CONFIG_WATCHDOG /* watchdog disabled */ 103#undef CONFIG_ALTIVEC /* undef to disable */ 104 105/* 106 * BOOTP options 107 */ 108#define CONFIG_BOOTP_SUBNETMASK 109#define CONFIG_BOOTP_GATEWAY 110#define CONFIG_BOOTP_HOSTNAME 111#define CONFIG_BOOTP_BOOTPATH 112#define CONFIG_BOOTP_BOOTFILESIZE 113 114#define CONFIG_MII /* enable MII commands */ 115 116 117/* 118 * Command line configuration. 119 */ 120#include <config_cmd_default.h> 121 122#define CONFIG_CMD_ASKENV 123#define CONFIG_CMD_BSP 124#define CONFIG_CMD_JFFS2 125#define CONFIG_CMD_MII 126#define CONFIG_CMD_DATE 127 128 129/* 130 * JFFS2 partitions 131 * 132 */ 133/* No command line, one static partition, whole device */ 134#undef CONFIG_CMD_MTDPARTS 135#define CONFIG_JFFS2_DEV "nor0" 136#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 137#define CONFIG_JFFS2_PART_OFFSET 0x00000000 138 139/* mtdparts command line support */ 140/* Note: fake mtd_id used, no linux mtd map file */ 141/* 142#define CONFIG_CMD_MTDPARTS 143#define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" 144#define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" 145*/ 146 147/* 148 * Miscellaneous configurable options 149 */ 150#define CONFIG_SYS_LONGHELP /* undef to save memory */ 151#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 152#if defined(CONFIG_CMD_KGDB) 153#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 154#else 155#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 156#endif 157#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 158#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 159#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 160 161#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 162#define CONFIG_SYS_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ 163 164#define CONFIG_SYS_LOAD_ADDR 0x00300000 /* default load address */ 165 166#define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */ 167 168#define CONFIG_SYS_BUS_CLK 133000000 /* 133 MHz */ 169 170#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 171 172/* 173 * Low Level Configuration Settings 174 * (address mappings, register initial values, etc.) 175 * You should know what you are doing if you make changes here. 176 */ 177 178/*----------------------------------------------------------------------- 179 * Definitions for initial stack pointer and data area 180 */ 181#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 182#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 184#define CONFIG_SYS_INIT_RAM_LOCK 185 186 187/*----------------------------------------------------------------------- 188 * Start addresses for the final memory configuration 189 * (Set up by the startup code) 190 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 191 */ 192#define CONFIG_SYS_SDRAM_BASE 0x00000000 193#define CONFIG_SYS_FLASH_BASE 0xfff00000 194#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 195#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 196#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 197#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 198 199/* areas to map different things with the GT in physical space */ 200#define CONFIG_SYS_DRAM_BANKS 4 201#define CONFIG_SYS_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */ 202 203/* What to put in the bats. */ 204#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 205 206/* Peripheral Device section */ 207#define CONFIG_SYS_GT_REGS 0xf8000000 /* later mapped GT_REGS */ 208#define CONFIG_SYS_DEV_BASE 0xf0000000 209#define CONFIG_SYS_DEV0_SIZE _64M /* zuma flash @ 0xf000.0000*/ 210#define CONFIG_SYS_DEV1_SIZE _8M /* zuma IDE @ 0xf400.0000 */ 211#define CONFIG_SYS_DEV2_SIZE _8M /* unused */ 212#define CONFIG_SYS_DEV3_SIZE _8M /* unused */ 213 214#define CONFIG_SYS_DEV0_PAR 0xc498243c 215 /* c 4 9 8 2 4 3 c */ 216 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ 217 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ 218 /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */ 219 /* 3| 0|.... ..| 1| 4 | 0 | 4 | 8 | 7 | 4 */ 220 221#define CONFIG_SYS_DEV1_PAR 0xc01b6ac5 222 /* c 0 1 b 6 a c 5 */ 223 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */ 224 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */ 225 /* 11|00|0000|00 01|101|1 01|10 1|010 1|100 0|101 */ 226 /* 3| 0|.... ..| 1| 5 | 5 | 5 | 5 | 8 | 5 */ 227 228 229#define CONFIG_SYS_8BIT_BOOT_PAR 0xc00b5e7c 230 231#define CONFIG_SYS_MPP_CONTROL_0 0x00007777 /* GPP[7:4] : REQ0[1:0] GNT0[1:0] */ 232#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 /* GPP[15:12] : GPP[11:8] */ 233#define CONFIG_SYS_MPP_CONTROL_2 0x00008888 /* GPP[23:20] : REQ1[1:0] GNT1[1:0] */ 234#define CONFIG_SYS_MPP_CONTROL_3 0x00000000 /* GPP[31:28] (int[3:0]) */ 235 /* GPP[27:24] (27 is int4, rest are GPP) */ 236 237#define CONFIG_SYS_SERIAL_PORT_MUX 0x00001101 /* 11=MPSC1/MPSC0 01=ETH, 0=only MII */ 238#define CONFIG_SYS_GPP_LEVEL_CONTROL 0xf8000000 /* interrupt inputs: GPP[31:27] */ 239 240#define CONFIG_SYS_SDRAM_CONFIG 0xe4e18200 /* 0x448 */ 241 /* idmas use buffer 1,1 242 comm use buffer 1 243 pci use buffer 0,0 (pci1->0 pci0->0) 244 cpu use buffer 1 (R*18) 245 normal load (see also ifdef HVL) 246 standard SDRAM (see also ifdef REG) 247 non staggered refresh */ 248 /* 31:26 25 23 20 19 18 16 */ 249 /* 111001 00 111 0 0 00 1 */ 250 251 /* refresh count=0x200 252 phy interleave disable (by default, 253 set later by dram config..) 254 virt interleave enable */ 255 /* 15 14 13:0 */ 256 /* 1 0 0x200 */ 257 258#define CONFIG_SYS_DEV0_SPACE CONFIG_SYS_DEV_BASE 259#define CONFIG_SYS_DEV1_SPACE (CONFIG_SYS_DEV0_SPACE + CONFIG_SYS_DEV0_SIZE) 260#define CONFIG_SYS_DEV2_SPACE (CONFIG_SYS_DEV1_SPACE + CONFIG_SYS_DEV1_SIZE) 261#define CONFIG_SYS_DEV3_SPACE (CONFIG_SYS_DEV2_SPACE + CONFIG_SYS_DEV2_SIZE) 262 263/*----------------------------------------------------------------------- 264 * PCI stuff 265 */ 266 267#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 268#define PCI_HOST_FORCE 1 /* configure as pci host */ 269#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 270 271#define CONFIG_PCI /* include pci support */ 272#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 273#define CONFIG_PCI_PNP /* do pci plug-and-play */ 274 275/* PCI MEMORY MAP section */ 276#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 277#define CONFIG_SYS_PCI0_MEM_SIZE _128M 278#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 279#define CONFIG_SYS_PCI1_MEM_SIZE _128M 280 281#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) 282#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) 283 284/* PCI I/O MAP section */ 285#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 286#define CONFIG_SYS_PCI0_IO_SIZE _16M 287#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 288#define CONFIG_SYS_PCI1_IO_SIZE _16M 289 290#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) 291#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 292#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) 293#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 294 295 296/*---------------------------------------------------------------------- 297 * Initial BAT mappings 298 */ 299 300/* NOTES: 301 * 1) GUARDED and WRITE_THRU not allowed in IBATS 302 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT 303 */ 304 305/* SDRAM */ 306#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 307#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 308#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 309#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 310 311/* init ram */ 312#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 313#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 314#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 315#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 316 317/* PCI0, PCI1 memory space (starting at PCI0 base, mapped in one BAT) */ 318#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS 319#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 320#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 321#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 322 323/* GT regs, bootrom, all the devices, PCI I/O */ 324#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) 325#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) 326#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 327#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 328 329/* 330 * For booting Linux, the board info and command line data 331 * have to be in the first 8 MB of memory, since this is 332 * the maximum mapped by the Linux kernel during initialization. 333 */ 334#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 335 336 337/*----------------------------------------------------------------------- 338 * FLASH organization 339 */ 340#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ 341#define CONFIG_SYS_MAX_FLASH_SECT 130 /* max number of sectors on one chip */ 342 343#define CONFIG_SYS_EXTRA_FLASH_DEVICE DEVICE0 /* extra flash at device 0 */ 344#define CONFIG_SYS_EXTRA_FLASH_WIDTH 2 /* 16 bit */ 345 346#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 347#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 348#define CONFIG_SYS_FLASH_CFI 1 349 350#define CONFIG_ENV_IS_IN_FLASH 1 351#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 352#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */ 353#define CONFIG_ENV_ADDR (0xfff80000 - CONFIG_ENV_SECT_SIZE) 354 355/*----------------------------------------------------------------------- 356 * Cache Configuration 357 */ 358#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 359#if defined(CONFIG_CMD_KGDB) 360#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 361#endif 362 363/*----------------------------------------------------------------------- 364 * L2CR setup -- make sure this is right for your board! 365 * look in include/74xx_7xx.h for the defines used here 366 */ 367 368#define CONFIG_SYS_L2 369 370#ifdef CONFIG_750CX 371#define L2_INIT 0 372#else 373#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 374 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 375#endif 376 377#define L2_ENABLE (L2_INIT | L2CR_L2E) 378 379/*------------------------------------------------------------------------ 380 * Real time clock 381 */ 382#define CONFIG_RTC_DS1302 383 384 385/*------------------------------------------------------------------------ 386 * Galileo I2C driver 387 */ 388#define CONFIG_GT_I2C 389 390#endif /* __CONFIG_H */ 391