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23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1
28#define CONFIG_4xx 1
29#define CONFIG_DLVISION_10G 1
30
31#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
32
33
34
35
36#define CONFIG_HOSTNAME dlvsion-10g
37#define CONFIG_IDENT_STRING " dlvision-10g 0.02"
38#include "amcc-common.h"
39
40#define CONFIG_BOARD_EARLY_INIT_F
41#define CONFIG_LAST_STAGE_INIT
42
43#define CONFIG_SYS_CLK_FREQ 33333333
44
45#undef CONFIG_ZERO_BOOTDELAY_CHECK
46#define CONFIG_AUTOBOOT_KEYED
47#define CONFIG_AUTOBOOT_STOP_STR " "
48
49
50
51
52#define PLLMR0_DEFAULT PLLMR0_266_133_66
53#define PLLMR1_DEFAULT PLLMR1_266_133_66
54
55
56#define CONFIG_FIT
57#define CONFIG_FIT_VERBOSE
58
59#define CONFIG_ENV_IS_IN_FLASH
60
61
62
63
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 CONFIG_AMCC_DEF_ENV \
66 CONFIG_AMCC_DEF_ENV_POWERPC \
67 CONFIG_AMCC_DEF_ENV_NOR_UPD \
68 "kernel_addr=fc000000\0" \
69 "fdt_addr=fc1e0000\0" \
70 "ramdisk_addr=fc200000\0" \
71 ""
72
73#define CONFIG_PHY_ADDR 4
74#define CONFIG_HAS_ETH0
75#define CONFIG_HAS_ETH1
76#define CONFIG_PHY1_ADDR 0xc
77#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
78
79
80
81
82#define CONFIG_CMD_CACHE
83#undef CONFIG_CMD_EEPROM
84
85
86
87
88#define CONFIG_SDRAM_BANK0 1
89
90
91#define CONFIG_SYS_SDRAM_CL 3
92#define CONFIG_SYS_SDRAM_tRP 20
93#define CONFIG_SYS_SDRAM_tRC 66
94#define CONFIG_SYS_SDRAM_tRCD 20
95#define CONFIG_SYS_SDRAM_tRFC 66
96
97
98
99
100
101
102
103
104
105
106#define CONFIG_CONS_INDEX 1
107#undef CONFIG_SYS_EXT_SERIAL_CLOCK
108#undef CONFIG_SYS_405_UART_ERRATA_59
109#define CONFIG_SYS_BASE_BAUD 691200
110
111
112
113
114#define CONFIG_SYS_I2C_SPEED 100000
115
116
117#define CONFIG_DTT_LM63 1
118#define CONFIG_DTT_SENSORS { 0x4c, 0x4e }
119#define CONFIG_DTT_PWM_LOOKUPTABLE \
120 { { 46, 10 }, { 48, 14 }, { 50, 19 }, { 52, 23 },\
121 { 54, 27 }, { 56, 31 }, { 58, 36 }, { 60, 40 } }
122#define CONFIG_DTT_TACH_LIMIT 0xa10
123
124
125
126#define CONFIG_SYS_FLASH_BASE 0xFC000000
127#define CONFIG_SYS_FPGA0_BASE 0x7f100000
128#define CONFIG_SYS_FPGA1_BASE 0x7f200000
129#define CONFIG_SYS_LATCH_BASE 0x7f300000
130
131#define CONFIG_SYS_FPGA_BASE(k) \
132 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
133
134#define CONFIG_SYS_FPGA_DONE(k) \
135 (k ? 0x2000 : 0x1000)
136
137#define CONFIG_SYS_FPGA_COUNT 2
138
139#define CONFIG_SYS_LATCH0_RESET 0xffff
140#define CONFIG_SYS_LATCH0_BOOT 0xffff
141#define CONFIG_SYS_LATCH1_RESET 0xffcf
142#define CONFIG_SYS_LATCH1_BOOT 0xffff
143
144#define CONFIG_SYS_FPGA_NO_RFL_HI
145
146
147
148
149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_FLASH_CFI_DRIVER
151
152#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
153
154#define CONFIG_SYS_MAX_FLASH_BANKS 1
155#define CONFIG_SYS_MAX_FLASH_SECT 512
156
157#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
158#define CONFIG_SYS_FLASH_WRITE_TOUT 500
159
160#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
161#define CONFIG_SYS_FLASH_PROTECTION 1
162
163#define CONFIG_SYS_FLASH_EMPTY_INFO
164#define CONFIG_SYS_FLASH_QUIET_TEST 1
165
166#ifdef CONFIG_ENV_IS_IN_FLASH
167#define CONFIG_ENV_SECT_SIZE 0x20000
168#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
169#define CONFIG_ENV_SIZE 0x2000
170
171
172#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
173#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
174#endif
175
176
177
178
179#define CONFIG_SYS_4xx_GPIO_TABLE { \
180{ \
181 \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
184{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
185{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
186{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
187{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
188{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
189{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
190{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
191{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
192{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
193{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
194{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
195{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
196{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
197{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
198{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
199{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
200{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
201{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
202{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
203{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
204{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
205{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
206{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
207{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
208{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
209{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
210{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
211{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
212{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
213{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
214} \
215}
216
217
218
219
220
221#define CONFIG_SYS_TEMP_STACK_OCM 1
222
223
224#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
225#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
226#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
227#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
228
229#define CONFIG_SYS_GBL_DATA_SIZE 128
230#define CONFIG_SYS_GBL_DATA_OFFSET \
231 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
232#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233
234
235
236
237
238
239#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_ENABLED | \
240 EBC_BXAP_FWT_ENCODE(8) | \
241 EBC_BXAP_BWT_ENCODE(7) | \
242 EBC_BXAP_BCE_DISABLE | \
243 EBC_BXAP_BCT_2TRANS | \
244 EBC_BXAP_CSN_ENCODE(0) | \
245 EBC_BXAP_OEN_ENCODE(2) | \
246 EBC_BXAP_WBN_ENCODE(2) | \
247 EBC_BXAP_WBF_ENCODE(2) | \
248 EBC_BXAP_TH_ENCODE(4) | \
249 EBC_BXAP_RE_DISABLED | \
250 EBC_BXAP_SOR_NONDELAYED | \
251 EBC_BXAP_BEM_WRITEONLY | \
252 EBC_BXAP_PEN_DISABLED)
253#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
254 EBC_BXCR_BS_64MB | \
255 EBC_BXCR_BU_RW | \
256 EBC_BXCR_BW_16BIT)
257
258
259#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
260 EBC_BXAP_TWT_ENCODE(5) | \
261 EBC_BXAP_BCE_DISABLE | \
262 EBC_BXAP_BCT_2TRANS | \
263 EBC_BXAP_CSN_ENCODE(0) | \
264 EBC_BXAP_OEN_ENCODE(2) | \
265 EBC_BXAP_WBN_ENCODE(1) | \
266 EBC_BXAP_WBF_ENCODE(1) | \
267 EBC_BXAP_TH_ENCODE(0) | \
268 EBC_BXAP_RE_DISABLED | \
269 EBC_BXAP_SOR_NONDELAYED | \
270 EBC_BXAP_BEM_WRITEONLY | \
271 EBC_BXAP_PEN_DISABLED)
272#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
273 EBC_BXCR_BS_1MB | \
274 EBC_BXCR_BU_RW | \
275 EBC_BXCR_BW_16BIT)
276
277
278#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
279 EBC_BXAP_TWT_ENCODE(6) | \
280 EBC_BXAP_BCE_DISABLE | \
281 EBC_BXAP_BCT_2TRANS | \
282 EBC_BXAP_CSN_ENCODE(0) | \
283 EBC_BXAP_OEN_ENCODE(2) | \
284 EBC_BXAP_WBN_ENCODE(1) | \
285 EBC_BXAP_WBF_ENCODE(1) | \
286 EBC_BXAP_TH_ENCODE(0) | \
287 EBC_BXAP_RE_DISABLED | \
288 EBC_BXAP_SOR_NONDELAYED | \
289 EBC_BXAP_BEM_WRITEONLY | \
290 EBC_BXAP_PEN_DISABLED)
291#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA1_BASE) | \
292 EBC_BXCR_BS_1MB | \
293 EBC_BXCR_BU_RW | \
294 EBC_BXCR_BW_16BIT)
295
296
297#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
298 EBC_BXAP_FWT_ENCODE(8) | \
299 EBC_BXAP_BWT_ENCODE(4) | \
300 EBC_BXAP_BCE_DISABLE | \
301 EBC_BXAP_BCT_2TRANS | \
302 EBC_BXAP_CSN_ENCODE(0) | \
303 EBC_BXAP_OEN_ENCODE(1) | \
304 EBC_BXAP_WBN_ENCODE(1) | \
305 EBC_BXAP_WBF_ENCODE(1) | \
306 EBC_BXAP_TH_ENCODE(2) | \
307 EBC_BXAP_RE_DISABLED | \
308 EBC_BXAP_SOR_NONDELAYED | \
309 EBC_BXAP_BEM_WRITEONLY | \
310 EBC_BXAP_PEN_DISABLED)
311#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
312 EBC_BXCR_BS_1MB | \
313 EBC_BXCR_BU_RW | \
314 EBC_BXCR_BW_16BIT)
315
316
317
318
319#define CONFIG_SYS_ICS8N3QV01
320#define CONFIG_SYS_MPC92469AC
321#define CONFIG_SYS_SIL1178
322#define CONFIG_SYS_OSD_SCREENS CONFIG_SYS_FPGA_COUNT
323
324#endif
325