LXR uboot/arch/arm/cpu/armv7/am33xx/board.c

   1/*
   2 * board.c
   3 *
   4 * Common board functions for AM33XX based boards
   5 *
   6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19#include <common.h>
  20#include <asm/arch/cpu.h>
  21#include <asm/arch/hardware.h>
  22#include <asm/arch/omap.h>
  23#include <asm/arch/ddr_defs.h>
  24#include <asm/arch/clock.h>
  25#include <asm/arch/mmc_host_def.h>
  26#include <asm/arch/common_def.h>
  27#include <asm/io.h>
  28#include <asm/omap_common.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
  33struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
  34struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
  35
  36/* UART Defines */
  37#ifdef CONFIG_SPL_BUILD
  38#define UART_RESET              (0x1 << 1)
  39#define UART_CLK_RUNNING_MASK   0x1
  40#define UART_SMART_IDLE_EN      (0x1 << 0x3)
  41#endif
  42
  43#ifdef CONFIG_SPL_BUILD
  44/* Initialize timer */
  45static void init_timer(void)
  46{
  47        /* Reset the Timer */
  48        writel(0x2, (&timer_base->tscir));
  49
  50        /* Wait until the reset is done */
  51        while (readl(&timer_base->tiocp_cfg) & 1)
  52                ;
  53
  54        /* Start the Timer */
  55        writel(0x1, (&timer_base->tclr));
  56}
  57#endif
  58
  59/*
  60 * early system init of muxing and clocks.
  61 */
  62void s_init(void)
  63{
  64        /* WDT1 is already running when the bootloader gets control
  65         * Disable it to avoid "random" resets
  66         */
  67        writel(0xAAAA, &wdtimer->wdtwspr);
  68        while (readl(&wdtimer->wdtwwps) != 0x0)
  69                ;
  70        writel(0x5555, &wdtimer->wdtwspr);
  71        while (readl(&wdtimer->wdtwwps) != 0x0)
  72                ;
  73
  74#ifdef CONFIG_SPL_BUILD
  75        /* Setup the PLLs and the clocks for the peripherals */
  76        pll_init();
  77
  78        /* UART softreset */
  79        u32 regVal;
  80
  81        enable_uart0_pin_mux();
  82
  83        regVal = readl(&uart_base->uartsyscfg);
  84        regVal |= UART_RESET;
  85        writel(regVal, &uart_base->uartsyscfg);
  86        while ((readl(&uart_base->uartsyssts) &
  87                UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
  88                ;
  89
  90        /* Disable smart idle */
  91        regVal = readl(&uart_base->uartsyscfg);
  92        regVal |= UART_SMART_IDLE_EN;
  93        writel(regVal, &uart_base->uartsyscfg);
  94
  95        /* Initialize the Timer */
  96        init_timer();
  97
  98        preloader_console_init();
  99
 100        config_ddr();
 101#endif
 102
 103        /* Enable MMC0 */
 104        enable_mmc0_pin_mux();
 105}
 106
 107#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 108int board_mmc_init(bd_t *bis)
 109{
 110        return omap_mmc_init(0, 0, 0);
 111}
 112#endif
 113
 114void setup_clocks_for_console(void)
 115{
 116        /* Not yet implemented */
 117        return;
 118}
 119