1/* 2 * emif4.c 3 * 4 * AM33XX emif4 configuration file 5 * 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <common.h> 20#include <asm/arch/cpu.h> 21#include <asm/arch/ddr_defs.h> 22#include <asm/arch/hardware.h> 23#include <asm/arch/clock.h> 24#include <asm/io.h> 25 26DECLARE_GLOBAL_DATA_PTR; 27 28struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR; 29struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; 30struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; 31 32 33int dram_init(void) 34{ 35 /* dram_init must store complete ramsize in gd->ram_size */ 36 gd->ram_size = get_ram_size( 37 (void *)CONFIG_SYS_SDRAM_BASE, 38 CONFIG_MAX_RAM_BANK_SIZE); 39 return 0; 40} 41 42void dram_init_banksize(void) 43{ 44 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 45 gd->bd->bi_dram[0].size = gd->ram_size; 46} 47 48 49#ifdef CONFIG_SPL_BUILD 50static void data_macro_config(int dataMacroNum) 51{ 52 struct ddr_data data; 53 54 data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) 55 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)); 56 data.datardsratio1 = DDR2_RD_DQS>>2; 57 data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) 58 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)); 59 data.datawdsratio1 = DDR2_WR_DQS>>2; 60 data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) 61 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)); 62 data.datawiratio1 = DDR2_PHY_WRLVL>>2; 63 data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) 64 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)); 65 data.datagiratio1 = DDR2_PHY_GATELVL>>2; 66 data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) 67 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)); 68 data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2; 69 data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) 70 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)); 71 data.datawrsratio1 = DDR2_PHY_WR_DATA>>2; 72 data.datadldiff0 = PHY_DLL_LOCK_DIFF; 73 74 config_ddr_data(dataMacroNum, &data); 75} 76 77static void cmd_macro_config(void) 78{ 79 struct cmd_control cmd; 80 81 cmd.cmd0csratio = DDR2_RATIO; 82 cmd.cmd0csforce = CMD_FORCE; 83 cmd.cmd0csdelay = CMD_DELAY; 84 cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF; 85 cmd.cmd0iclkout = DDR2_INVERT_CLKOUT; 86 87 cmd.cmd1csratio = DDR2_RATIO; 88 cmd.cmd1csforce = CMD_FORCE; 89 cmd.cmd1csdelay = CMD_DELAY; 90 cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF; 91 cmd.cmd1iclkout = DDR2_INVERT_CLKOUT; 92 93 cmd.cmd2csratio = DDR2_RATIO; 94 cmd.cmd2csforce = CMD_FORCE; 95 cmd.cmd2csdelay = CMD_DELAY; 96 cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF; 97 cmd.cmd2iclkout = DDR2_INVERT_CLKOUT; 98 99 config_cmd_ctrl(&cmd); 100 101} 102 103static void config_vtp(void) 104{ 105 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, 106 &vtpreg->vtp0ctrlreg); 107 writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN), 108 &vtpreg->vtp0ctrlreg); 109 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN, 110 &vtpreg->vtp0ctrlreg); 111 112 /* Poll for READY */ 113 while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) != 114 VTP_CTRL_READY) 115 ; 116} 117 118static void config_emif_ddr2(void) 119{ 120 int i; 121 int ret; 122 struct sdram_config cfg; 123 struct sdram_timing tmg; 124 struct ddr_phy_control phyc; 125 126 /*Program EMIF0 CFG Registers*/ 127 phyc.reg = EMIF_READ_LATENCY; 128 phyc.reg_sh = EMIF_READ_LATENCY; 129 phyc.reg2 = EMIF_READ_LATENCY; 130 131 tmg.time1 = EMIF_TIM1; 132 tmg.time1_sh = EMIF_TIM1; 133 tmg.time2 = EMIF_TIM2; 134 tmg.time2_sh = EMIF_TIM2; 135 tmg.time3 = EMIF_TIM3; 136 tmg.time3_sh = EMIF_TIM3; 137 138 cfg.sdrcr = EMIF_SDCFG; 139 cfg.sdrcr2 = EMIF_SDCFG; 140 cfg.refresh = 0x00004650; 141 cfg.refresh_sh = 0x00004650; 142 143 /* Program EMIF instance */ 144 ret = config_ddr_phy(&phyc); 145 if (ret < 0) 146 printf("Couldn't configure phyc\n"); 147 148 ret = config_sdram(&cfg); 149 if (ret < 0) 150 printf("Couldn't configure SDRAM\n"); 151 152 ret = set_sdram_timings(&tmg); 153 if (ret < 0) 154 printf("Couldn't configure timings\n"); 155 156 /* Delay */ 157 for (i = 0; i < 5000; i++) 158 ; 159 160 cfg.refresh = EMIF_SDREF; 161 cfg.refresh_sh = EMIF_SDREF; 162 cfg.sdrcr = EMIF_SDCFG; 163 cfg.sdrcr2 = EMIF_SDCFG; 164 165 ret = config_sdram(&cfg); 166 if (ret < 0) 167 printf("Couldn't configure SDRAM\n"); 168} 169 170void config_ddr(void) 171{ 172 int data_macro_0 = 0; 173 int data_macro_1 = 1; 174 struct ddr_ioctrl ioctrl; 175 176 enable_emif_clocks(); 177 178 config_vtp(); 179 180 cmd_macro_config(); 181 182 data_macro_config(data_macro_0); 183 data_macro_config(data_macro_1); 184 185 writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0); 186 writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0); 187 188 ioctrl.cmd1ctl = DDR_IOCTRL_VALUE; 189 ioctrl.cmd2ctl = DDR_IOCTRL_VALUE; 190 ioctrl.cmd3ctl = DDR_IOCTRL_VALUE; 191 ioctrl.data1ctl = DDR_IOCTRL_VALUE; 192 ioctrl.data2ctl = DDR_IOCTRL_VALUE; 193 194 config_io_ctrl(&ioctrl); 195 196 writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl); 197 writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl); 198 199 config_emif_ddr2(); 200} 201#endif 202