LXR uboot/arch/blackfin/include/asm/mach-bf518/BF514

   1/* DO NOT EDIT THIS FILE
   2 * Automatically generated by generate-def-headers.xsl
   3 * DO NOT EDIT THIS FILE
   4 */
   5
   6#ifndef __BFIN_DEF_ADSP_BF514_proc__
   7#define __BFIN_DEF_ADSP_BF514_proc__
   8
   9#include "BF512_def.h"
  10
  11#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
  12#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
  13#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
  14#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
  15#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
  16#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
  17#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
  18#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
  19#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
  20#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
  21#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
  22#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
  23#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
  24#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
  25#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
  26#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
  27#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
  28#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
  29#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
  30#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
  31#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
  32#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
  33#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
  34#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
  35#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
  36#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
  37#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
  38#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
  39
  40#endif /* __BFIN_DEF_ADSP_BF514_proc__ */
  41