1/* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6#ifndef __BFIN_DEF_ADSP_EDN_core__ 7#define __BFIN_DEF_ADSP_EDN_core__ 8 9#define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */ 10#define DMEM_CONTROL 0xFFE00004 /* Data memory control */ 11#define DCPLB_FAULT_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */ 12#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */ 13#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */ 14#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */ 15#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */ 16#define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */ 17#define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */ 18#define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */ 19#define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */ 20#define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */ 21#define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */ 22#define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */ 23#define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */ 24#define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */ 25#define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */ 26#define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */ 27#define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */ 28#define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */ 29#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */ 30#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */ 31#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */ 32#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */ 33#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */ 34#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */ 35#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */ 36#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */ 37#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */ 38#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */ 39#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */ 40#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */ 41#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */ 42#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */ 43#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */ 44#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */ 45#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */ 46#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */ 47#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */ 48 49#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */ 50#define ICPLB_FAULT_STATUS 0xFFE01008 /* Instruction Cache Programmable Look-Aside Buffer Status */ 51#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache Programmable Look-Aside Buffer Fault Address */ 52#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */ 53#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */ 54#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */ 55#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */ 56#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */ 57#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */ 58#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */ 59#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */ 60#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */ 61#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */ 62#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */ 63#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */ 64#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */ 65#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */ 66#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */ 67#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */ 68#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */ 69#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */ 70#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */ 71#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */ 72#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */ 73#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */ 74#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */ 75#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */ 76#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */ 77#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */ 78#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */ 79#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */ 80#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */ 81#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */ 82#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */ 83#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */ 84#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */ 85#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */ 86#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */ 87 88#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */ 89#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */ 90#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */ 91#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */ 92#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */ 93#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */ 94#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */ 95#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */ 96#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */ 97#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */ 98#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */ 99#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */ 100#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */ 101#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */ 102#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */ 103#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */ 104 105#define EVT_OVERRIDE 0xFFE02100 106#define ILAT 0xFFE0210C /* Interrupt Latch Register */ 107#define IMASK 0xFFE02104 /* Interrupt Mask Register */ 108#define IPEND 0xFFE02108 /* Interrupt Pending Register */ 109#define IPRIO 0xFFE02110 /* Interrupt Priority Register */ 110 111#define TCNTL 0xFFE03000 /* Core Timer Control Register */ 112#define TPERIOD 0xFFE03004 /* Core Timer Period Register */ 113#define TSCALE 0xFFE03008 /* Core Timer Scale Register */ 114#define TCOUNT 0xFFE0300C /* Core Timer Count Register */ 115 116#define DSPID 0xFFE05000 117#define DBGSTAT 0xFFE05008 118 119#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */ 120#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */ 121#define TBUF 0xFFE06100 /* Trace Buffer */ 122 123#define WPIACTL 0xFFE07000 124#define WPIA0 0xFFE07040 125#define WPIA1 0xFFE07044 126#define WPIA2 0xFFE07048 127#define WPIA3 0xFFE0704C 128#define WPIA4 0xFFE07050 129#define WPIA5 0xFFE07054 130#define WPIACNT0 0xFFE07080 131#define WPIACNT1 0xFFE07084 132#define WPIACNT2 0xFFE07088 133#define WPIACNT3 0xFFE0708C 134#define WPIACNT4 0xFFE07090 135#define WPIACNT5 0xFFE07094 136#define WPDACTL 0xFFE07100 137#define WPDA0 0xFFE07140 138#define WPDA1 0xFFE07144 139#define WPDACNT0 0xFFE07180 140#define WPDACNT1 0xFFE07184 141#define WPSTAT 0xFFE07200 142 143#define PFCTL 0xFFE08000 144#define PFCNTR0 0xFFE08100 145#define PFCNTR1 0xFFE08104 146 147#endif /* __BFIN_DEF_ADSP_EDN_core__ */ 148