1/* 2 * MCF5329 Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __IMMAP_5235__ 27#define __IMMAP_5235__ 28 29#define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) 30#define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) 31#define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) 32#define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) 33#define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) 34#define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) 35#define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) 36#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) 37#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) 38#define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) 39#define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) 40#define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) 41#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) 42#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) 43#define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) 44#define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) 45#define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) 46#define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) 47#define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) 48#define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) 49#define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) 50#define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) 51#define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) 52#define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) 53#define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) 54#define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) 55#define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) 56#define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) 57#define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) 58#define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) 59#define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) 60#define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) 61#define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) 62#define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) 63#define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) 64#define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) 65 66#include <asm/coldfire/eport.h> 67#include <asm/coldfire/flexbus.h> 68#include <asm/coldfire/flexcan.h> 69#include <asm/coldfire/intctrl.h> 70#include <asm/coldfire/mdha.h> 71#include <asm/coldfire/qspi.h> 72#include <asm/coldfire/rng.h> 73#include <asm/coldfire/skha.h> 74 75/* System Control Module register */ 76typedef struct scm_ctrl { 77 u32 ipsbar; /* 0x00 - MBAR */ 78 u32 res1; /* 0x04 */ 79 u32 rambar; /* 0x08 - RAMBAR */ 80 u32 res2; /* 0x0C */ 81 u8 crsr; /* 0x10 Core Reset Status Register */ 82 u8 cwcr; /* 0x11 Core Watchdog Control Register */ 83 u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ 84 u8 cwsr; /* 0x13 Core Watchdog Service Register */ 85 u32 dmareqc; /* 0x14 */ 86 u32 res3; /* 0x18 */ 87 u32 mpark; /* 0x1C */ 88 u8 mpr; /* 0x20 */ 89 u8 res4[3]; /* 0x21 - 0x23 */ 90 u8 pacr0; /* 0x24 */ 91 u8 pacr1; /* 0x25 */ 92 u8 pacr2; /* 0x26 */ 93 u8 pacr3; /* 0x27 */ 94 u8 pacr4; /* 0x28 */ 95 u32 res5; /* 0x29 */ 96 u8 pacr5; /* 0x2a */ 97 u8 pacr6; /* 0x2b */ 98 u8 pacr7; /* 0x2c */ 99 u32 res6; /* 0x2d */ 100 u8 pacr8; /* 0x2e */ 101 u32 res7; /* 0x2f */ 102 u8 gpacr; /* 0x30 */ 103 u8 res8[3]; /* 0x31 - 0x33 */ 104} scm_t; 105 106/* SDRAM controller registers */ 107typedef struct sdram_ctrl { 108 u16 dcr; /* 0x00 Control register */ 109 u16 res1[3]; /* 0x02 - 0x07 */ 110 u32 dacr0; /* 0x08 address and control register 0 */ 111 u32 dmr0; /* 0x0C mask register block 0 */ 112 u32 dacr1; /* 0x10 address and control register 1 */ 113 u32 dmr1; /* 0x14 mask register block 1 */ 114} sdram_t; 115 116typedef struct canex_ctrl { 117 can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ 118} canex_t; 119 120/* GPIO port registers */ 121typedef struct gpio_ctrl { 122 /* Port Output Data Registers */ 123 u8 podr_addr; /* 0x00 */ 124 u8 podr_datah; /* 0x01 */ 125 u8 podr_datal; /* 0x02 */ 126 u8 podr_busctl; /* 0x03 */ 127 u8 podr_bs; /* 0x04 */ 128 u8 podr_cs; /* 0x05 */ 129 u8 podr_sdram; /* 0x06 */ 130 u8 podr_feci2c; /* 0x07 */ 131 u8 podr_uarth; /* 0x08 */ 132 u8 podr_uartl; /* 0x09 */ 133 u8 podr_qspi; /* 0x0A */ 134 u8 podr_timer; /* 0x0B */ 135 u8 podr_etpu; /* 0x0C */ 136 u8 res1[3]; /* 0x0D - 0x0F */ 137 138 /* Port Data Direction Registers */ 139 u8 pddr_addr; /* 0x10 */ 140 u8 pddr_datah; /* 0x11 */ 141 u8 pddr_datal; /* 0x12 */ 142 u8 pddr_busctl; /* 0x13 */ 143 u8 pddr_bs; /* 0x14 */ 144 u8 pddr_cs; /* 0x15 */ 145 u8 pddr_sdram; /* 0x16 */ 146 u8 pddr_feci2c; /* 0x17 */ 147 u8 pddr_uarth; /* 0x18 */ 148 u8 pddr_uartl; /* 0x19 */ 149 u8 pddr_qspi; /* 0x1A */ 150 u8 pddr_timer; /* 0x1B */ 151 u8 pddr_etpu; /* 0x1C */ 152 u8 res2[3]; /* 0x1D - 0x1F */ 153 154 /* Port Data Direction Registers */ 155 u8 ppdsdr_addr; /* 0x20 */ 156 u8 ppdsdr_datah; /* 0x21 */ 157 u8 ppdsdr_datal; /* 0x22 */ 158 u8 ppdsdr_busctl; /* 0x23 */ 159 u8 ppdsdr_bs; /* 0x24 */ 160 u8 ppdsdr_cs; /* 0x25 */ 161 u8 ppdsdr_sdram; /* 0x26 */ 162 u8 ppdsdr_feci2c; /* 0x27 */ 163 u8 ppdsdr_uarth; /* 0x28 */ 164 u8 ppdsdr_uartl; /* 0x29 */ 165 u8 ppdsdr_qspi; /* 0x2A */ 166 u8 ppdsdr_timer; /* 0x2B */ 167 u8 ppdsdr_etpu; /* 0x2C */ 168 u8 res3[3]; /* 0x2D - 0x2F */ 169 170 /* Port Clear Output Data Registers */ 171 u8 pclrr_addr; /* 0x30 */ 172 u8 pclrr_datah; /* 0x31 */ 173 u8 pclrr_datal; /* 0x32 */ 174 u8 pclrr_busctl; /* 0x33 */ 175 u8 pclrr_bs; /* 0x34 */ 176 u8 pclrr_cs; /* 0x35 */ 177 u8 pclrr_sdram; /* 0x36 */ 178 u8 pclrr_feci2c; /* 0x37 */ 179 u8 pclrr_uarth; /* 0x38 */ 180 u8 pclrr_uartl; /* 0x39 */ 181 u8 pclrr_qspi; /* 0x3A */ 182 u8 pclrr_timer; /* 0x3B */ 183 u8 pclrr_etpu; /* 0x3C */ 184 u8 res4[3]; /* 0x3D - 0x3F */ 185 186 /* Pin Assignment Registers */ 187 u8 par_ad; /* 0x40 */ 188 u8 res5; /* 0x41 */ 189 u16 par_busctl; /* 0x42 */ 190 u8 par_bs; /* 0x44 */ 191 u8 par_cs; /* 0x45 */ 192 u8 par_sdram; /* 0x46 */ 193 u8 par_feci2c; /* 0x47 */ 194 u16 par_uart; /* 0x48 */ 195 u8 par_qspi; /* 0x4A */ 196 u8 res6; /* 0x4B */ 197 u16 par_timer; /* 0x4C */ 198 u8 par_etpu; /* 0x4E */ 199 u8 res7; /* 0x4F */ 200 201 /* Drive Strength Control Registers */ 202 u8 dscr_eim; /* 0x50 */ 203 u8 dscr_etpu; /* 0x51 */ 204 u8 dscr_feci2c; /* 0x52 */ 205 u8 dscr_uart; /* 0x53 */ 206 u8 dscr_qspi; /* 0x54 */ 207 u8 dscr_timer; /* 0x55 */ 208 u16 res8; /* 0x56 */ 209} gpio_t; 210 211/*Chip configuration module registers */ 212typedef struct ccm_ctrl { 213 u8 rcr; /* 0x01 */ 214 u8 rsr; /* 0x02 */ 215 u16 res1; /* 0x03 */ 216 u16 ccr; /* 0x04 Chip configuration register */ 217 u16 lpcr; /* 0x06 Low-power Control register */ 218 u16 rcon; /* 0x08 Rreset configuration register */ 219 u16 cir; /* 0x0a Chip identification register */ 220} ccm_t; 221 222/* Clock Module registers */ 223typedef struct pll_ctrl { 224 u32 syncr; /* 0x00 synthesizer control register */ 225 u32 synsr; /* 0x04 synthesizer status register */ 226} pll_t; 227 228/* Watchdog registers */ 229typedef struct wdog_ctrl { 230 u16 cr; /* 0x00 Control register */ 231 u16 mr; /* 0x02 Modulus register */ 232 u16 cntr; /* 0x04 Count register */ 233 u16 sr; /* 0x06 Service register */ 234} wdog_t; 235 236#endif /* __IMMAP_5235__ */ 237