1/* 2 * MCF5445x Internal Memory Map 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __IMMAP_5445X__ 27#define __IMMAP_5445X__ 28 29/* Module Base Addresses */ 30#define MMAP_SCM1 0xFC000000 31#define MMAP_XBS 0xFC004000 32#define MMAP_FBCS 0xFC008000 33#define MMAP_FEC0 0xFC030000 34#define MMAP_FEC1 0xFC034000 35#define MMAP_RTC 0xFC03C000 36#define MMAP_SCM2 0xFC040000 37#define MMAP_EDMA 0xFC044000 38#define MMAP_INTC0 0xFC048000 39#define MMAP_INTC1 0xFC04C000 40#define MMAP_IACK 0xFC054000 41#define MMAP_I2C 0xFC058000 42#define MMAP_DSPI 0xFC05C000 43#define MMAP_UART0 0xFC060000 44#define MMAP_UART1 0xFC064000 45#define MMAP_UART2 0xFC068000 46#define MMAP_DTMR0 0xFC070000 47#define MMAP_DTMR1 0xFC074000 48#define MMAP_DTMR2 0xFC078000 49#define MMAP_DTMR3 0xFC07C000 50#define MMAP_PIT0 0xFC080000 51#define MMAP_PIT1 0xFC084000 52#define MMAP_PIT2 0xFC088000 53#define MMAP_PIT3 0xFC08C000 54#define MMAP_EPORT 0xFC094000 55#define MMAP_WTM 0xFC098000 56#define MMAP_SBF 0xFC0A0000 57#define MMAP_RCM 0xFC0A0000 58#define MMAP_CCM 0xFC0A0000 59#define MMAP_GPIO 0xFC0A4000 60#define MMAP_PCI 0xFC0A8000 61#define MMAP_PCIARB 0xFC0AC000 62#define MMAP_RNG 0xFC0B4000 63#define MMAP_SDRAM 0xFC0B8000 64#define MMAP_SSI 0xFC0BC000 65#define MMAP_PLL 0xFC0C4000 66#define MMAP_ATA 0x90000000 67#define MMAP_USBHW 0xFC0B0000 68#define MMAP_USBCAPS 0xFC0B0100 69#define MMAP_USBEHCI 0xFC0B0140 70#define MMAP_USBOTG 0xFC0B01A0 71 72#include <asm/coldfire/ata.h> 73#include <asm/coldfire/crossbar.h> 74#include <asm/coldfire/dspi.h> 75#include <asm/coldfire/edma.h> 76#include <asm/coldfire/eport.h> 77#include <asm/coldfire/flexbus.h> 78#include <asm/coldfire/intctrl.h> 79#include <asm/coldfire/ssi.h> 80 81/* Watchdog Timer Modules (WTM) */ 82typedef struct wtm { 83 u16 wcr; 84 u16 wmr; 85 u16 wcntr; 86 u16 wsr; 87} wtm_t; 88 89/* Serial Boot Facility (SBF) */ 90typedef struct sbf { 91 u8 resv0[0x18]; 92 u16 sbfsr; /* Serial Boot Facility Status Register */ 93 u8 resv1[0x6]; 94 u16 sbfcr; /* Serial Boot Facility Control Register */ 95} sbf_t; 96 97/* Reset Controller Module (RCM) */ 98typedef struct rcm { 99 u8 rcr; 100 u8 rsr; 101} rcm_t; 102 103/* Chip Configuration Module (CCM) */ 104typedef struct ccm { 105 u8 ccm_resv0[0x4]; 106 u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */ 107 u8 resv1[0x2]; 108 u16 rcon; /* Reset Configuration (256 TEPBGA, Read-only) */ 109 u16 cir; /* Chip Identification Register (Read-only) */ 110 u8 resv2[0x4]; 111 u16 misccr; /* Miscellaneous Control Register */ 112 u16 cdr; /* Clock Divider Register */ 113 u16 uocsr; /* USB On-the-Go Controller Status Register */ 114} ccm_t; 115 116/* General Purpose I/O Module (GPIO) */ 117typedef struct gpio { 118 u8 podr_fec0h; /* FEC0 High Port Output Data Register */ 119 u8 podr_fec0l; /* FEC0 Low Port Output Data Register */ 120 u8 podr_ssi; /* SSI Port Output Data Register */ 121 u8 podr_fbctl; /* Flexbus Control Port Output Data Register */ 122 u8 podr_be; /* Flexbus Byte Enable Port Output Data Register */ 123 u8 podr_cs; /* Flexbus Chip-Select Port Output Data Register */ 124 u8 podr_dma; /* DMA Port Output Data Register */ 125 u8 podr_feci2c; /* FEC1 / I2C Port Output Data Register */ 126 u8 resv0[0x1]; 127 u8 podr_uart; /* UART Port Output Data Register */ 128 u8 podr_dspi; /* DSPI Port Output Data Register */ 129 u8 podr_timer; /* Timer Port Output Data Register */ 130 u8 podr_pci; /* PCI Port Output Data Register */ 131 u8 podr_usb; /* USB Port Output Data Register */ 132 u8 podr_atah; /* ATA High Port Output Data Register */ 133 u8 podr_atal; /* ATA Low Port Output Data Register */ 134 u8 podr_fec1h; /* FEC1 High Port Output Data Register */ 135 u8 podr_fec1l; /* FEC1 Low Port Output Data Register */ 136 u8 resv1[0x2]; 137 u8 podr_fbadh; /* Flexbus AD High Port Output Data Register */ 138 u8 podr_fbadmh; /* Flexbus AD Med-High Port Output Data Register */ 139 u8 podr_fbadml; /* Flexbus AD Med-Low Port Output Data Register */ 140 u8 podr_fbadl; /* Flexbus AD Low Port Output Data Register */ 141 u8 pddr_fec0h; /* FEC0 High Port Data Direction Register */ 142 u8 pddr_fec0l; /* FEC0 Low Port Data Direction Register */ 143 u8 pddr_ssi; /* SSI Port Data Direction Register */ 144 u8 pddr_fbctl; /* Flexbus Control Port Data Direction Register */ 145 u8 pddr_be; /* Flexbus Byte Enable Port Data Direction Register */ 146 u8 pddr_cs; /* Flexbus Chip-Select Port Data Direction Register */ 147 u8 pddr_dma; /* DMA Port Data Direction Register */ 148 u8 pddr_feci2c; /* FEC1 / I2C Port Data Direction Register */ 149 u8 resv2[0x1]; 150 u8 pddr_uart; /* UART Port Data Direction Register */ 151 u8 pddr_dspi; /* DSPI Port Data Direction Register */ 152 u8 pddr_timer; /* Timer Port Data Direction Register */ 153 u8 pddr_pci; /* PCI Port Data Direction Register */ 154 u8 pddr_usb; /* USB Port Data Direction Register */ 155 u8 pddr_atah; /* ATA High Port Data Direction Register */ 156 u8 pddr_atal; /* ATA Low Port Data Direction Register */ 157 u8 pddr_fec1h; /* FEC1 High Port Data Direction Register */ 158 u8 pddr_fec1l; /* FEC1 Low Port Data Direction Register */ 159 u8 resv3[0x2]; 160 u8 pddr_fbadh; /* Flexbus AD High Port Data Direction Register */ 161 u8 pddr_fbadmh; /* Flexbus AD Med-High Port Data Direction Register */ 162 u8 pddr_fbadml; /* Flexbus AD Med-Low Port Data Direction Register */ 163 u8 pddr_fbadl; /* Flexbus AD Low Port Data Direction Register */ 164 u8 ppdsdr_fec0h; /* FEC0 High Port Pin Data/Set Data Register */ 165 u8 ppdsdr_fec0l; /* FEC0 Low Port Clear Output Data Register */ 166 u8 ppdsdr_ssi; /* SSI Port Pin Data/Set Data Register */ 167 u8 ppdsdr_fbctl; /* Flexbus Control Port Pin Data/Set Data Register */ 168 u8 ppdsdr_be; /* Flexbus Byte Enable Port Pin Data/Set Data Register */ 169 u8 ppdsdr_cs; /* Flexbus Chip-Select Port Pin Data/Set Data Register */ 170 u8 ppdsdr_dma; /* DMA Port Pin Data/Set Data Register */ 171 u8 ppdsdr_feci2c; /* FEC1 / I2C Port Pin Data/Set Data Register */ 172 u8 resv4[0x1]; 173 u8 ppdsdr_uart; /* UART Port Pin Data/Set Data Register */ 174 u8 ppdsdr_dspi; /* DSPI Port Pin Data/Set Data Register */ 175 u8 ppdsdr_timer; /* FTimer Port Pin Data/Set Data Register */ 176 u8 ppdsdr_pci; /* PCI Port Pin Data/Set Data Register */ 177 u8 ppdsdr_usb; /* USB Port Pin Data/Set Data Register */ 178 u8 ppdsdr_atah; /* ATA High Port Pin Data/Set Data Register */ 179 u8 ppdsdr_atal; /* ATA Low Port Pin Data/Set Data Register */ 180 u8 ppdsdr_fec1h; /* FEC1 High Port Pin Data/Set Data Register */ 181 u8 ppdsdr_fec1l; /* FEC1 Low Port Pin Data/Set Data Register */ 182 u8 resv5[0x2]; 183 u8 ppdsdr_fbadh; /* Flexbus AD High Port Pin Data/Set Data Register */ 184 u8 ppdsdr_fbadmh; /* Flexbus AD Med-High Port Pin Data/Set Data Register */ 185 u8 ppdsdr_fbadml; /* Flexbus AD Med-Low Port Pin Data/Set Data Register */ 186 u8 ppdsdr_fbadl; /* Flexbus AD Low Port Pin Data/Set Data Register */ 187 u8 pclrr_fec0h; /* FEC0 High Port Clear Output Data Register */ 188 u8 pclrr_fec0l; /* FEC0 Low Port Pin Data/Set Data Register */ 189 u8 pclrr_ssi; /* SSI Port Clear Output Data Register */ 190 u8 pclrr_fbctl; /* Flexbus Control Port Clear Output Data Register */ 191 u8 pclrr_be; /* Flexbus Byte Enable Port Clear Output Data Register */ 192 u8 pclrr_cs; /* Flexbus Chip-Select Port Clear Output Data Register */ 193 u8 pclrr_dma; /* DMA Port Clear Output Data Register */ 194 u8 pclrr_feci2c; /* FEC1 / I2C Port Clear Output Data Register */ 195 u8 resv6[0x1]; 196 u8 pclrr_uart; /* UART Port Clear Output Data Register */ 197 u8 pclrr_dspi; /* DSPI Port Clear Output Data Register */ 198 u8 pclrr_timer; /* Timer Port Clear Output Data Register */ 199 u8 pclrr_pci; /* PCI Port Clear Output Data Register */ 200 u8 pclrr_usb; /* USB Port Clear Output Data Register */ 201 u8 pclrr_atah; /* ATA High Port Clear Output Data Register */ 202 u8 pclrr_atal; /* ATA Low Port Clear Output Data Register */ 203 u8 pclrr_fec1h; /* FEC1 High Port Clear Output Data Register */ 204 u8 pclrr_fec1l; /* FEC1 Low Port Clear Output Data Register */ 205 u8 resv7[0x2]; 206 u8 pclrr_fbadh; /* Flexbus AD High Port Clear Output Data Register */ 207 u8 pclrr_fbadmh; /* Flexbus AD Med-High Port Clear Output Data Register */ 208 u8 pclrr_fbadml; /* Flexbus AD Med-Low Port Clear Output Data Register */ 209 u8 pclrr_fbadl; /* Flexbus AD Low Port Clear Output Data Register */ 210 u8 par_fec; /* FEC Pin Assignment Register */ 211 u8 par_dma; /* DMA Pin Assignment Register */ 212 u8 par_fbctl; /* Flexbus Control Pin Assignment Register */ 213 u8 par_dspi; /* DSPI Pin Assignment Register */ 214 u8 par_be; /* Flexbus Byte-Enable Pin Assignment Register */ 215 u8 par_cs; /* Flexbus Chip-Select Pin Assignment Register */ 216 u8 par_timer; /* Time Pin Assignment Register */ 217 u8 par_usb; /* USB Pin Assignment Register */ 218 u8 resv8[0x1]; 219 u8 par_uart; /* UART Pin Assignment Register */ 220 u16 par_feci2c; /* FEC / I2C Pin Assignment Register */ 221 u16 par_ssi; /* SSI Pin Assignment Register */ 222 u16 par_ata; /* ATA Pin Assignment Register */ 223 u8 par_irq; /* IRQ Pin Assignment Register */ 224 u8 resv9[0x1]; 225 u16 par_pci; /* PCI Pin Assignment Register */ 226 u8 mscr_sdram; /* SDRAM Mode Select Control Register */ 227 u8 mscr_pci; /* PCI Mode Select Control Register */ 228 u8 resv10[0x2]; 229 u8 dscr_i2c; /* I2C Drive Strength Control Register */ 230 u8 dscr_flexbus; /* FLEXBUS Drive Strength Control Register */ 231 u8 dscr_fec; /* FEC Drive Strength Control Register */ 232 u8 dscr_uart; /* UART Drive Strength Control Register */ 233 u8 dscr_dspi; /* DSPI Drive Strength Control Register */ 234 u8 dscr_timer; /* TIMER Drive Strength Control Register */ 235 u8 dscr_ssi; /* SSI Drive Strength Control Register */ 236 u8 dscr_dma; /* DMA Drive Strength Control Register */ 237 u8 dscr_debug; /* DEBUG Drive Strength Control Register */ 238 u8 dscr_reset; /* RESET Drive Strength Control Register */ 239 u8 dscr_irq; /* IRQ Drive Strength Control Register */ 240 u8 dscr_usb; /* USB Drive Strength Control Register */ 241 u8 dscr_ata; /* ATA Drive Strength Control Register */ 242} gpio_t; 243 244/* SDRAM Controller (SDRAMC) */ 245typedef struct sdramc { 246 u32 sdmr; /* SDRAM Mode/Extended Mode Register */ 247 u32 sdcr; /* SDRAM Control Register */ 248 u32 sdcfg1; /* SDRAM Configuration Register 1 */ 249 u32 sdcfg2; /* SDRAM Chip Select Register */ 250 u8 resv0[0x100]; 251 u32 sdcs0; /* SDRAM Mode/Extended Mode Register */ 252 u32 sdcs1; /* SDRAM Mode/Extended Mode Register */ 253} sdramc_t; 254 255/* Phase Locked Loop (PLL) */ 256typedef struct pll { 257 u32 pcr; /* PLL Control Register */ 258 u32 psr; /* PLL Status Register */ 259} pll_t; 260 261typedef struct pci { 262 u32 idr; /* 0x00 Device Id / Vendor Id Register */ 263 u32 scr; /* 0x04 Status / command Register */ 264 u32 ccrir; /* 0x08 Class Code / Revision Id Register */ 265 u32 cr1; /* 0x0c Configuration 1 Register */ 266 u32 bar0; /* 0x10 Base address register 0 Register */ 267 u32 bar1; /* 0x14 Base address register 1 Register */ 268 u32 bar2; /* 0x18 Base address register 2 Register */ 269 u32 bar3; /* 0x1c Base address register 3 Register */ 270 u32 bar4; /* 0x20 Base address register 4 Register */ 271 u32 bar5; /* 0x24 Base address register 5 Register */ 272 u32 ccpr; /* 0x28 Cardbus CIS Pointer Register */ 273 u32 sid; /* 0x2c Subsystem ID / Subsystem Vendor ID Register */ 274 u32 erbar; /* 0x30 Expansion ROM Base Address Register */ 275 u32 cpr; /* 0x34 Capabilities Pointer Register */ 276 u32 rsvd1; /* 0x38 */ 277 u32 cr2; /* 0x3c Configuration Register 2 */ 278 u32 rsvd2[8]; /* 0x40 - 0x5f */ 279 280 /* General control / status registers */ 281 u32 gscr; /* 0x60 Global Status / Control Register */ 282 u32 tbatr0a; /* 0x64 Target Base Address Translation Register 0 */ 283 u32 tbatr1a; /* 0x68 Target Base Address Translation Register 1 */ 284 u32 tcr1; /* 0x6c Target Control 1 Register */ 285 u32 iw0btar; /* 0x70 Initiator Window 0 Base/Translation addr */ 286 u32 iw1btar; /* 0x74 Initiator Window 1 Base/Translation addr */ 287 u32 iw2btar; /* 0x78 Initiator Window 2 Base/Translation addr */ 288 u32 rsvd3; /* 0x7c */ 289 u32 iwcr; /* 0x80 Initiator Window Configuration Register */ 290 u32 icr; /* 0x84 Initiator Control Register */ 291 u32 isr; /* 0x88 Initiator Status Register */ 292 u32 tcr2; /* 0x8c Target Control 2 Register */ 293 u32 tbatr0; /* 0x90 Target Base Address Translation Register 0 */ 294 u32 tbatr1; /* 0x94 Target Base Address Translation Register 1 */ 295 u32 tbatr2; /* 0x98 Target Base Address Translation Register 2 */ 296 u32 tbatr3; /* 0x9c Target Base Address Translation Register 3 */ 297 u32 tbatr4; /* 0xa0 Target Base Address Translation Register 4 */ 298 u32 tbatr5; /* 0xa4 Target Base Address Translation Register 5 */ 299 u32 intr; /* 0xa8 Interrupt Register */ 300 u32 rsvd4[19]; /* 0xac - 0xf7 */ 301 u32 car; /* 0xf8 Configuration Address Register */ 302} pci_t; 303 304typedef struct pci_arbiter { 305 /* Pci Arbiter Registers */ 306 union { 307 u32 acr; /* Arbiter Control Register */ 308 u32 asr; /* Arbiter Status Register */ 309 }; 310} pciarb_t; 311 312/* Register read/write struct */ 313typedef struct scm1 { 314 u32 mpr; /* 0x00 Master Privilege Register */ 315 u32 rsvd1[7]; 316 u32 pacra; /* 0x20 Peripheral Access Control Register A */ 317 u32 pacrb; /* 0x24 Peripheral Access Control Register B */ 318 u32 pacrc; /* 0x28 Peripheral Access Control Register C */ 319 u32 pacrd; /* 0x2C Peripheral Access Control Register D */ 320 u32 rsvd2[4]; 321 u32 pacre; /* 0x40 Peripheral Access Control Register E */ 322 u32 pacrf; /* 0x44 Peripheral Access Control Register F */ 323 u32 pacrg; /* 0x48 Peripheral Access Control Register G */ 324} scm1_t; 325 326typedef struct scm2 { 327 u8 rsvd1[19]; /* 0x00 - 0x12 */ 328 u8 wcr; /* 0x13 */ 329 u16 rsvd2; /* 0x14 - 0x15 */ 330 u16 cwcr; /* 0x16 */ 331 u8 rsvd3[3]; /* 0x18 - 0x1A */ 332 u8 cwsr; /* 0x1B */ 333 u8 rsvd4[3]; /* 0x1C - 0x1E */ 334 u8 scmisr; /* 0x1F */ 335 u32 rsvd5; /* 0x20 - 0x23 */ 336 u8 bcr; /* 0x24 */ 337 u8 rsvd6[74]; /* 0x25 - 0x6F */ 338 u32 cfadr; /* 0x70 */ 339 u8 rsvd7; /* 0x74 */ 340 u8 cfier; /* 0x75 */ 341 u8 cfloc; /* 0x76 */ 342 u8 cfatr; /* 0x77 */ 343 u32 rsvd8; /* 0x78 - 0x7B */ 344 u32 cfdtr; /* 0x7C */ 345} scm2_t; 346 347typedef struct rtcex { 348 u32 rsvd1[3]; 349 u32 gocu; 350 u32 gocl; 351} rtcex_t; 352#endif /* __IMMAP_5445X__ */ 353