1/* 2 * (C) Copyright 2010 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21#ifndef _PPC440GP_H_ 22#define _PPC440GP_H_ 23 24#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ 25 26/* 27 * Some SoC specific registers (not common for all 440 SoC's) 28 */ 29 30/* Memory mapped register */ 31#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */ 32 33#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) 34#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) 35 36#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) 37 38#define SDR0_PCI0 0x0300 39 40#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) 41#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) 42 43#define CNTRL_DCR_BASE 0x0b0 44 45#define CPC0_SYS0 (CNTRL_DCR_BASE + 0x30) /* System configuration reg 0 */ 46#define CPC0_SYS1 (CNTRL_DCR_BASE + 0x31) /* System configuration reg 1 */ 47 48#define CPC0_STRP0 (CNTRL_DCR_BASE + 0x34) /* Power-on config reg 0 (RO) */ 49#define CPC0_STRP1 (CNTRL_DCR_BASE + 0x35) /* Power-on config reg 1 (RO) */ 50 51#define CPC0_GPIO (CNTRL_DCR_BASE + 0x38) /* GPIO config reg (440GP) */ 52 53#define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */ 54#define CPC0_CR1 (CNTRL_DCR_BASE + 0x3a) /* Control 1 register */ 55 56#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ 57#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ 58#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ 59#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ 60#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ 61#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ 62#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ 63#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ 64#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ 65#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ 66#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ 67#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ 68 69#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) 70#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) 71 72#endif /* _PPC440GP_H_ */ 73