1/* 2 * (C) Copyright 2008 3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Panel: 640x480 50Hz TFT Single 18-bit (PCLK=20.000 MHz) 26 * Memory: DRAM (MCLK=40.000 MHz) 27 */ 28static S1D_REGS regs_13505_640_480_16bpp[] = 29{ 30 {0x1B,0x00}, /* Miscellaneous Register */ 31 {0x23,0x20}, /* Performance Enhancement Register 1 */ 32 {0x01,0x30}, /* Memory Configuration Register */ 33 {0x22,0x24}, /* Performance Enhancement Register 0 */ 34 {0x02,0x25}, /* Panel Type Register */ 35 {0x03,0x00}, /* MOD Rate Register */ 36 {0x04,0x4F}, /* Horizontal Display Width Register */ 37 {0x05,0x0c}, /* Horizontal Non-Display Period Register */ 38 {0x06,0x00}, /* HRTC/FPLINE Start Position Register */ 39 {0x07,0x01}, /* HRTC/FPLINE Pulse Width Register */ 40 {0x08,0xDF}, /* Vertical Display Height Register 0 */ 41 {0x09,0x01}, /* Vertical Display Height Register 1 */ 42 {0x0A,0x3E}, /* Vertical Non-Display Period Register */ 43 {0x0B,0x00}, /* VRTC/FPFRAME Start Position Register */ 44 {0x0C,0x01}, /* VRTC/FPFRAME Pulse Width Register */ 45 {0x0E,0xFF}, /* Screen 1 Line Compare Register 0 */ 46 {0x0F,0x03}, /* Screen 1 Line Compare Register 1 */ 47 {0x10,0x00}, /* Screen 1 Display Start Address Register 0 */ 48 {0x11,0x00}, /* Screen 1 Display Start Address Register 1 */ 49 {0x12,0x00}, /* Screen 1 Display Start Address Register 2 */ 50 {0x13,0x00}, /* Screen 2 Display Start Address Register 0 */ 51 {0x14,0x00}, /* Screen 2 Display Start Address Register 1 */ 52 {0x15,0x00}, /* Screen 2 Display Start Address Register 2 */ 53 {0x16,0x80}, /* Memory Address Offset Register 0 */ 54 {0x17,0x02}, /* Memory Address Offset Register 1 */ 55 {0x18,0x00}, /* Pixel Panning Register */ 56 {0x19,0x01}, /* Clock Configuration Register */ 57 {0x1A,0x00}, /* Power Save Configuration Register */ 58 {0x1C,0x00}, /* MD Configuration Readback Register 0 */ 59 {0x1E,0x06}, /* General IO Pins Configuration Register 0 */ 60 {0x1F,0x00}, /* General IO Pins Configuration Register 1 */ 61 {0x20,0x00}, /* General IO Pins Control Register 0 */ 62 {0x21,0x00}, /* General IO Pins Control Register 1 */ 63 {0x23,0x20}, /* Performance Enhancement Register 1 */ 64 {0x0D,0x15}, /* Display Mode Register */ 65}; 66