LXR uboot/board/esd/cpci2dp/cpci2dp.c

   1/*
   2 * (C) Copyright 2005
   3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/processor.h>
  26#include <asm/io.h>
  27#include <command.h>
  28#include <malloc.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32int board_early_init_f (void)
  33{
  34        unsigned long CPC0_CR0Reg;
  35
  36        /*
  37         * Setup GPIO pins
  38         */
  39        CPC0_CR0Reg = mfdcr(CPC0_CR0);
  40        mtdcr(CPC0_CR0, CPC0_CR0Reg |
  41              ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED |
  42                CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
  43
  44        /* set output pins to high */
  45        out_be32((void *)GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
  46        /* setup for output (LED=off) */
  47        out_be32((void *)GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
  48
  49        /*
  50         * IRQ 0-15  405GP internally generated; active high; level sensitive
  51         * IRQ 16    405GP internally generated; active low; level sensitive
  52         * IRQ 17-24 RESERVED
  53         * IRQ 25 (EXT IRQ 0) PB0; active low; level sensitive
  54         * IRQ 26 (EXT IRQ 1) PB1; active low; level sensitive
  55         * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
  56         * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
  57         * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  58         * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
  59         * IRQ 31 (EXT IRQ 6) unused
  60         */
  61        mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  62        mtdcr(UIC0ER, 0x00000000);      /* disable all ints */
  63        mtdcr(UIC0CR, 0x00000000);      /* set all to be non-critical*/
  64        mtdcr(UIC0PR, 0xFFFFFF81);      /* set int polarities */
  65
  66        mtdcr(UIC0TR, 0x10000000);      /* set int trigger levels */
  67        mtdcr(UIC0VCR, 0x00000001);     /* set vect base=0,INT0 highest priority*/
  68        mtdcr(UIC0SR, 0xFFFFFFFF);      /* clear all ints */
  69
  70        return 0;
  71}
  72
  73int misc_init_r (void)
  74{
  75        unsigned long CPC0_CR0Reg;
  76
  77        /* adjust flash start and offset */
  78        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  79        gd->bd->bi_flashoffset = 0;
  80
  81        /*
  82         * Select cts (and not dsr) on uart1
  83         */
  84        CPC0_CR0Reg = mfdcr(CPC0_CR0);
  85        mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
  86
  87        return (0);
  88}
  89
  90
  91/*
  92 * Check Board Identity:
  93 */
  94int checkboard (void)
  95{
  96        char str[64];
  97        int i = getenv_f("serial#", str, sizeof(str));
  98
  99        puts ("Board: ");
 100
 101        if (i == -1) {
 102                puts ("### No HW ID - assuming CPCI2DP");
 103        } else {
 104                puts(str);
 105        }
 106
 107        printf(" (Ver 1.0)");
 108
 109        putc ('\n');
 110
 111        return 0;
 112}
 113
 114#if defined(CONFIG_SYS_EEPROM_WREN)
 115/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 116 *         <state>     -1: deliver current state
 117 *                     0: disable write
 118 *                     1: enable write
 119 *  Returns:           -1: wrong device address
 120 *                      0: dis-/en- able done
 121 *                   0/1: current state if <state> was -1.
 122 */
 123int eeprom_write_enable (unsigned dev_addr, int state) {
 124        if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 125                return -1;
 126        } else {
 127                switch (state) {
 128                case 1:
 129                        /* Enable write access, clear bit GPIO_SINT2. */
 130                        out_be32((void *)GPIO0_OR,
 131                                 in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 132                        state = 0;
 133                        break;
 134                case 0:
 135                        /* Disable write access, set bit GPIO_SINT2. */
 136                        out_be32((void *)GPIO0_OR,
 137                                 in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 138                        state = 0;
 139                        break;
 140                default:
 141                        /* Read current status back. */
 142                        state = (0 == (in_be32((void *)GPIO0_OR) &
 143                                       CONFIG_SYS_EEPROM_WP));
 144                        break;
 145                }
 146        }
 147        return state;
 148}
 149#endif
 150
 151#if defined(CONFIG_SYS_EEPROM_WREN)
 152int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 153{
 154        int query = argc == 1;
 155        int state = 0;
 156
 157        if (query) {
 158                /* Query write access state. */
 159                state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 160                if (state < 0) {
 161                        puts ("Query of write access state failed.\n");
 162                } else {
 163                        printf ("Write access for device 0x%0x is %sabled.\n",
 164                                CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 165                        state = 0;
 166                }
 167        } else {
 168                if ('0' == argv[1][0]) {
 169                        /* Disable write access. */
 170                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 171                } else {
 172                        /* Enable write access. */
 173                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 174                }
 175                if (state < 0) {
 176                        puts ("Setup of write access state failed.\n");
 177                }
 178        }
 179
 180        return state;
 181}
 182
 183U_BOOT_CMD(
 184        eepwren,        2,      0,      do_eep_wren,
 185        "Enable / disable / query EEPROM write access",
 186        ""
 187);
 188#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 189