LXR uboot/board/esd/pmc440/pmc440.h

   1/*
   2 * (C) Copyright 2007-2008
   3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#ifndef __PMC440_H__
  25#define __PMC440_H__
  26
  27/*
  28 * GPIOs
  29 */
  30#define GPIO1_INTA_FAKE           (0x80000000 >> (45-32)) /* GPIO45 OD */
  31#define GPIO1_NONMONARCH          (0x80000000 >> (63-32)) /* GPIO63 I */
  32#define GPIO1_PPC_EREADY          (0x80000000 >> (62-32)) /* GPIO62 I/O */
  33#define GPIO1_M66EN               (0x80000000 >> (61-32)) /* GPIO61 I */
  34#define GPIO1_POST_N              (0x80000000 >> (60-32)) /* GPIO60 O */
  35#define GPIO1_IOEN_N              (0x80000000 >> (50-32)) /* GPIO50 O */
  36#define GPIO1_HWID_MASK           (0xf0000000 >> (56-32)) /* GPIO56..59 I */
  37
  38#define GPIO1_USB_PWR_N           (0x80000000 >> (32-32)) /* GPIO32 I */
  39#define GPIO0_LED_RUN_N           (0x80000000 >> 30)      /* GPIO30 O */
  40#define GPIO0_EP_EEP              (0x80000000 >> 23)      /* GPIO23 O */
  41#define GPIO0_USB_ID              (0x80000000 >> 21)      /* GPIO21 I */
  42#define GPIO0_USB_PRSNT           (0x80000000 >> 20)      /* GPIO20 I */
  43
  44/*
  45 * FPGA programming pin configuration
  46 */
  47#define GPIO1_FPGA_PRG            (0x80000000 >> (53-32)) /* FPGA program pin (ppc output) */
  48#define GPIO1_FPGA_CLK            (0x80000000 >> (51-32)) /* FPGA clk pin (ppc output)     */
  49#define GPIO1_FPGA_DATA           (0x80000000 >> (52-32)) /* FPGA data pin (ppc output)    */
  50#define GPIO1_FPGA_DONE           (0x80000000 >> (55-32)) /* FPGA done pin (ppc input)     */
  51#define GPIO1_FPGA_INIT           (0x80000000 >> (54-32)) /* FPGA init pin (ppc input)     */
  52#define GPIO0_FPGA_FORCEINIT      (0x80000000 >> 27)      /* low: force INIT# low */
  53
  54/*
  55 * FPGA interface
  56 */
  57#define FPGA_BA CONFIG_SYS_FPGA_BASE0
  58#define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
  59#define FPGA_IN32(p) in_be32((void*)(p))
  60#define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
  61#define FPGA_CLRBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) & ~(v))
  62
  63struct pmc440_fifo_s {
  64        u32 data;
  65        u32 ctrl;
  66};
  67
  68/* fifo ctrl register */
  69#define FIFO_IE              (1 << 15)
  70#define FIFO_OVERFLOW        (1 << 10)
  71#define FIFO_EMPTY           (1 <<  9)
  72#define FIFO_FULL            (1 <<  8)
  73#define FIFO_LEVEL_MASK      0x000000ff
  74
  75#define FIFO_COUNT           4
  76
  77struct pmc440_fpga_s {
  78        u32 ctrla;
  79        u32 status;
  80        u32 ctrlb;
  81        u32 pad1[0x40 / sizeof(u32) - 3];
  82        u32 irig_time;                  /* offset: 0x0040 */
  83        u32 irig_tod;
  84        u32 irig_cf;
  85        u32 pad2;
  86        u32 irig_rx_time;               /* offset: 0x0050 */
  87        u32 pad3[3];
  88        u32 hostctrl;                   /* offset: 0x0060 */
  89        u32 pad4[0x20 / sizeof(u32) - 1];
  90        struct pmc440_fifo_s fifo[FIFO_COUNT]; /* 0x0080..0x009f */
  91};
  92
  93typedef struct pmc440_fpga_s pmc440_fpga_t;
  94
  95/* ctrl register */
  96#define CTRL_HOST_IE         (1 <<  8)
  97
  98/* outputs */
  99#define RESET_EN    (1 << 31)
 100#define CLOCK_EN    (1 << 30)
 101#define RESET_OUT   (1 << 19)
 102#define CLOCK_OUT   (1 << 22)
 103#define RESET_OUT   (1 << 19)
 104#define IRIGB_R_OUT (1 << 14)
 105
 106/* status register */
 107#define STATUS_VERSION_SHIFT 24
 108#define STATUS_VERSION_MASK  0xff000000
 109#define STATUS_HWREV_SHIFT   20
 110#define STATUS_HWREV_MASK    0x00f00000
 111
 112#define STATUS_CAN_ISF       (1 << 11)
 113#define STATUS_CSTM_ISF      (1 << 10)
 114#define STATUS_FIFO_ISF      (1 <<  9)
 115#define STATUS_HOST_ISF      (1 <<  8)
 116
 117/* inputs */
 118#define RESET_IN    (1 << 0)
 119#define CLOCK_IN    (1 << 1)
 120#define IRIGB_R_IN  (1 << 5)
 121
 122/* hostctrl register */
 123#define HOSTCTRL_PMCRSTOUT_GATE (1 <<  17)
 124#define HOSTCTRL_PMCRSTOUT_FLAG (1 <<  16)
 125#define HOSTCTRL_CSTM1IE_GATE (1 <<  7)
 126#define HOSTCTRL_CSTM1IW_FLAG (1 <<  6)
 127#define HOSTCTRL_CSTM0IE_GATE (1 <<  5)
 128#define HOSTCTRL_CSTM0IW_FLAG (1 <<  4)
 129#define HOSTCTRL_FIFOIE_GATE (1 <<  3)
 130#define HOSTCTRL_FIFOIE_FLAG (1 <<  2)
 131#define HOSTCTRL_HCINT_GATE  (1 <<  1)
 132#define HOSTCTRL_HCINT_FLAG  (1 <<  0)
 133
 134#define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
 135#define NGCC_CTRL_FPGARST_N    (1 <<  2)
 136
 137/*
 138 * FPGA to PPC interrupt
 139 */
 140#define IRQ0_FPGA            (32+28) /* UIC1 - FPGA internal */
 141#define IRQ1_FPGA            (32+30) /* UIC1 - custom module */
 142#define IRQ2_FPGA            (64+ 3) /* UIC2 - custom module / CAN */
 143#define IRQ_ETH0             (64+ 4) /* UIC2 */
 144#define IRQ_ETH1             (   27) /* UIC0 */
 145#define IRQ_RTC              (64+ 0) /* UIC2 */
 146#define IRQ_PCIA             (64+ 1) /* UIC2 */
 147#define IRQ_PCIB             (32+18) /* UIC1 */
 148#define IRQ_PCIC             (32+19) /* UIC1 */
 149#define IRQ_PCID             (32+20) /* UIC1 */
 150
 151#endif /* __PMC440_H__ */
 152