LXR uboot/board/esd/voh405/voh405.c

   1/*
   2 * (C) Copyright 2001-2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/io.h>
  26#include <asm/processor.h>
  27#include <command.h>
  28#include <malloc.h>
  29
  30/* ------------------------------------------------------------------------- */
  31
  32#if 0
  33#define FPGA_DEBUG
  34#endif
  35
  36extern void lxt971_no_sleep(void);
  37
  38/* fpga configuration data - gzip compressed and generated by bin2c */
  39const unsigned char fpgadata[] =
  40{
  41#include "fpgadata.c"
  42};
  43
  44/*
  45 * include common fpga code (for esd boards)
  46 */
  47#include "../common/fpga.c"
  48
  49
  50/* logo bitmap data - gzip compressed and generated by bin2c */
  51unsigned char logo_bmp_320[] =
  52{
  53#include "logo_320_240_4bpp.c"
  54};
  55
  56unsigned char logo_bmp_640[] =
  57{
  58#include "logo_640_480_24bpp.c"
  59};
  60
  61
  62/*
  63 * include common lcd code (for esd boards)
  64 */
  65#include "../common/lcd.c"
  66
  67#include "../common/s1d13704_320_240_4bpp.h"
  68#include "../common/s1d13806_320_240_4bpp.h"
  69#include "../common/s1d13806_640_480_16bpp.h"
  70
  71
  72int board_early_init_f (void)
  73{
  74        /*
  75         * IRQ 0-15  405GP internally generated; active high; level sensitive
  76         * IRQ 16    405GP internally generated; active low; level sensitive
  77         * IRQ 17-24 RESERVED
  78         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  79         * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  80         * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  81         * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  82         * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  83         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  84         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  85         */
  86        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  87        mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  88        mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  89        mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
  90        mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  91        mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  92        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  93
  94        /*
  95         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  96         */
  97        mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
  98
  99        return 0;
 100}
 101
 102int misc_init_r (void)
 103{
 104        unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 105        unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 106        unsigned short *lcd_contrast =
 107                (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
 108        unsigned short *lcd_backlight =
 109                (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
 110        unsigned char *dst;
 111        ulong len = sizeof(fpgadata);
 112        int status;
 113        int index;
 114        int i;
 115        char *str;
 116
 117        dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 118        if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 119                printf ("GUNZIP ERROR - must RESET board to recover\n");
 120                do_reset (NULL, 0, 0, NULL);
 121        }
 122
 123        status = fpga_boot(dst, len);
 124        if (status != 0) {
 125                printf("\nFPGA: Booting failed ");
 126                switch (status) {
 127                case ERROR_FPGA_PRG_INIT_LOW:
 128                        printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 129                        break;
 130                case ERROR_FPGA_PRG_INIT_HIGH:
 131                        printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 132                        break;
 133                case ERROR_FPGA_PRG_DONE:
 134                        printf("(Timeout: DONE not high after programming FPGA)\n ");
 135                        break;
 136                }
 137
 138                /* display infos on fpgaimage */
 139                index = 15;
 140                for (i=0; i<4; i++) {
 141                        len = dst[index];
 142                        printf("FPGA: %s\n", &(dst[index+1]));
 143                        index += len+3;
 144                }
 145                putc ('\n');
 146                /* delayed reboot */
 147                for (i=20; i>0; i--) {
 148                        printf("Rebooting in %2d seconds \r",i);
 149                        for (index=0;index<1000;index++)
 150                                udelay(1000);
 151                }
 152                putc ('\n');
 153                do_reset(NULL, 0, 0, NULL);
 154        }
 155
 156        puts("FPGA:  ");
 157
 158        /* display infos on fpgaimage */
 159        index = 15;
 160        for (i=0; i<4; i++) {
 161                len = dst[index];
 162                printf("%s ", &(dst[index+1]));
 163                index += len+3;
 164        }
 165        putc ('\n');
 166
 167        free(dst);
 168
 169        /*
 170         * Reset FPGA via FPGA_INIT pin
 171         */
 172        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 173        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 174        udelay(1000); /* wait 1ms */
 175        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
 176        udelay(1000); /* wait 1ms */
 177
 178        /*
 179         * Reset external DUARTs
 180         */
 181        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 182        udelay(10); /* wait 10us */
 183        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 184        udelay(1000); /* wait 1ms */
 185
 186        /*
 187         * Set NAND-FLASH GPIO signals to default
 188         */
 189        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 190        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 191
 192        /*
 193         * Setup EEPROM write protection
 194         */
 195        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 196        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 197
 198        /*
 199         * Enable interrupts in exar duart mcr[3]
 200         */
 201        out_8(duart0_mcr, 0x08);
 202        out_8(duart1_mcr, 0x08);
 203
 204        /*
 205         * Init lcd interface and display logo
 206         */
 207        str = getenv("bd_type");
 208        if (strcmp(str, "voh405_bw") == 0) {
 209                lcd_setup(0, 1);
 210                lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 211                         regs_13704_320_240_4bpp,
 212                         sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 213                         logo_bmp_320, sizeof(logo_bmp_320));
 214        } else if (strcmp(str, "voh405_bwbw") == 0) {
 215                lcd_setup(0, 1);
 216                lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 217                         regs_13704_320_240_4bpp,
 218                         sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 219                         logo_bmp_320, sizeof(logo_bmp_320));
 220                lcd_setup(1, 1);
 221                lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 222                         regs_13806_320_240_4bpp,
 223                         sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
 224                         logo_bmp_320, sizeof(logo_bmp_320));
 225        } else if (strcmp(str, "voh405_bwc") == 0) {
 226                lcd_setup(0, 1);
 227                lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 228                         regs_13704_320_240_4bpp,
 229                         sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 230                         logo_bmp_320, sizeof(logo_bmp_320));
 231                lcd_setup(1, 0);
 232                lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 233                         regs_13806_640_480_16bpp,
 234                         sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 235                         logo_bmp_640, sizeof(logo_bmp_640));
 236        } else {
 237                printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 238                return 0;
 239        }
 240
 241        /*
 242         * Set invert bit in small lcd controller
 243         */
 244        out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
 245              in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
 246
 247        /*
 248         * Set default contrast voltage on epson vga controller
 249         */
 250        out_be16(lcd_contrast, 0x4646);
 251
 252        /*
 253         * Enable backlight
 254         */
 255        out_be16(lcd_backlight, 0xffff);
 256
 257        /*
 258         * Enable external I2C bus
 259         */
 260        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
 261
 262        return (0);
 263}
 264
 265
 266/*
 267 * Check Board Identity:
 268 */
 269
 270int checkboard (void)
 271{
 272        char str[64];
 273        int i = getenv_f("serial#", str, sizeof(str));
 274
 275        puts ("Board: ");
 276
 277        if (i == -1) {
 278                puts ("### No HW ID - assuming VOH405");
 279        } else {
 280                puts(str);
 281        }
 282
 283        if (getenv_f("bd_type", str, sizeof(str)) != -1) {
 284                printf(" (%s)", str);
 285        } else {
 286                puts(" (Missing bd_type!)");
 287        }
 288
 289        putc ('\n');
 290
 291        return 0;
 292}
 293
 294#ifdef CONFIG_IDE_RESET
 295#define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 296void ide_set_reset(int on)
 297{
 298        /*
 299         * Assert or deassert CompactFlash Reset Pin
 300         */
 301        if (on) {               /* assert RESET */
 302                out_be16((void *)FPGA_MODE,
 303                         in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 304        } else {                /* release RESET */
 305                out_be16((void *)FPGA_MODE,
 306                         in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 307        }
 308}
 309#endif /* CONFIG_IDE_RESET */
 310
 311#if defined(CONFIG_RESET_PHY_R)
 312void reset_phy(void)
 313{
 314#ifdef CONFIG_LXT971_NO_SLEEP
 315
 316        /*
 317         * Disable sleep mode in LXT971
 318         */
 319        lxt971_no_sleep();
 320#endif
 321}
 322#endif
 323
 324#if defined(CONFIG_SYS_EEPROM_WREN)
 325/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 326 *         <state>     -1: deliver current state
 327 *                     0: disable write
 328 *                     1: enable write
 329 *  Returns:           -1: wrong device address
 330 *                      0: dis-/en- able done
 331 *                   0/1: current state if <state> was -1.
 332 */
 333int eeprom_write_enable (unsigned dev_addr, int state)
 334{
 335        if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 336                return -1;
 337        } else {
 338                switch (state) {
 339                case 1:
 340                        /* Enable write access, clear bit GPIO0. */
 341                        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 342                        state = 0;
 343                        break;
 344                case 0:
 345                        /* Disable write access, set bit GPIO0. */
 346                        out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 347                        state = 0;
 348                        break;
 349                default:
 350                        /* Read current status back. */
 351                        state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 352                        break;
 353                }
 354        }
 355        return state;
 356}
 357
 358int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 359{
 360        int query = argc == 1;
 361        int state = 0;
 362
 363        if (query) {
 364                /* Query write access state. */
 365                state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 366                if (state < 0) {
 367                        puts ("Query of write access state failed.\n");
 368                } else {
 369                        printf ("Write access for device 0x%0x is %sabled.\n",
 370                                CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 371                        state = 0;
 372                }
 373        } else {
 374                if ('0' == argv[1][0]) {
 375                        /* Disable write access. */
 376                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 377                } else {
 378                        /* Enable write access. */
 379                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 380                }
 381                if (state < 0) {
 382                        puts ("Setup of write access state failed.\n");
 383                }
 384        }
 385
 386        return state;
 387}
 388
 389U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 390        "Enable / disable / query EEPROM write access",
 391        ""
 392);
 393#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 394